From 74ded5884f09ee3b73cf8a6347a2ac806582a16d Mon Sep 17 00:00:00 2001 From: Jimmy Zheng Date: Wed, 31 Jul 2024 14:39:51 +0800 Subject: [PATCH] tests: kernel: gen_isr_table: add available IRQ number for AE350 CLIC RISC-V CLIC can trigger edge-triggered interrupts by software, but the available IRQ sources depend on the hardware implementation. Clarifies the IRQ source for GD32VF103 and adds support for AE350 CLIC. Signed-off-by: Jimmy Zheng --- tests/kernel/gen_isr_table/src/main.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/kernel/gen_isr_table/src/main.c index 343165bd25f..22517051016 100644 --- a/tests/kernel/gen_isr_table/src/main.c +++ b/tests/kernel/gen_isr_table/src/main.c @@ -46,15 +46,20 @@ extern const uintptr_t _irq_vector_table[]; #error "Target not supported" #endif -#elif defined(CONFIG_RISCV_HAS_CLIC) +#elif defined(CONFIG_SOC_GD32VF103) #define ISR1_OFFSET 3 #define ISR3_OFFSET 17 #define ISR5_OFFSET 18 #define TRIG_CHECK_SIZE 19 +#elif defined(CONFIG_SOC_ANDES_AE350_CLIC) +#define ISR1_OFFSET 19 +#define ISR3_OFFSET 20 +#define ISR5_OFFSET 21 +#define TRIG_CHECK_SIZE 22 #else #if !defined(IRQ1_USED) -/* RISC-V has very few IRQ lines which can be triggered from software */ +/* RISC-V CLINT has very few IRQ lines which can be triggered from software */ #define ISR3_OFFSET 1 #endif