zephyr/arch/riscv/core
Krzysztof Chruściński 4026daa42e arch: riscv: Add support for CPU load measuring
Add sys_trace_idle_exit to RISCV cpu_idle functions and allow
enabling CPU_LOAD module for RISCV and disable it for SMP.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-03-20 17:14:52 +01:00
..
offsets arch: riscv: handle interrupt level for CLIC 2025-02-05 17:48:45 +01:00
asm_macros.inc
CMakeLists.txt
coredump.c
cpu_idle.c arch: riscv: Add support for CPU load measuring 2025-03-20 17:14:52 +01:00
elf.c llext: avoid direct llext_string() usage 2025-03-17 19:58:15 +01:00
fatal.c arch: riscv: Rename _Fault to z_riscv_fault 2025-01-28 23:42:06 +01:00
fpu.c
fpu.S
ipi_clint.c
ipi.c
irq_manage.c
irq_offload.c
isr.S arch: riscv: handle interrupt level for CLIC 2025-02-05 17:48:45 +01:00
pmp.c
pmp.S
prep_c.c
reboot.c
reset.S
semihost.c
smp.c
stacktrace.c
switch.S
thread.c arch: riscv: handle interrupt level for CLIC 2025-02-05 17:48:45 +01:00
tls.c
userspace.S
vector_table.ld