Francois Ramu 9f7eba2044 dts: bindings: clock stm32g4 has a PLL P divider ... The PLL div-p for the stm32g4x has more possible value than stm32l4 possible ra nge is from 2 to 31 Signed-off-by: Francois Ramu <francois.ramu@st.com>		2022-03-23 09:25:47 -05:00
..
arc	everywhere: fix typos	2022-03-14 20:22:24 -04:00
arm	dts: arm: rpi_pico: added resets for UART instances	2022-03-23 12:51:39 +01:00
arm64	nxp: imx: support i.MX8MP EVK board	2022-03-14 11:28:35 +01:00
bindings	dts: bindings: clock stm32g4 has a PLL P divider	2022-03-23 09:25:47 -05:00
common	dts/arm: stm32: Add clocks nodes on stm32wb,l4 and stm32f4 series	2021-04-27 11:53:37 +02:00
nios2	dts: rename 'nios2,i2c' compatible to 'altr,nios2-i2c'	2021-08-17 17:51:57 -04:00
posix
riscv	ITE drivers/kscan: use wakeup interface for WUC pins	2022-03-21 16:35:03 -07:00
sparc	dts: sparc: add cpus node to leon3	2022-01-11 10:46:20 +01:00
x86	dts/x86: Add VT-D node on Elkhart Lake	2022-01-07 10:47:27 -05:00
xtensa	soc/intel_adsp: add support for Intel Jasper Lake	2022-03-10 09:26:41 -06:00
binding-template.yaml	doc: devicetree: overhaul bindings guide	2021-04-22 15:32:10 +02:00
Kconfig