nxp: imx: support i.MX8MP EVK board

Support i.MX8MP EVK A53 with/without jailhouse hypervisor
 - Add dts/dtsi
 - Add board file

Signed-off-by: Peng Fan <peng.fan@nxp.com>

CODEOWNERS

@@ -179,6 +179,7 @@
 /boards/arm64/qemu_cortex_a53/            @carlocaione
 /boards/arm64/bcm958402m2_a72/            @abhishek-brcm
 /boards/arm64/imx8mm_evk/                 @MrVan
+/boards/arm64/imx8mp_evk/                 @MrVan
 /boards/arm64/nxp_ls1046ardb/             @JiafeiPan
 /boards/arm64/xenvm/                      @lorc @firscity
 /boards/arm64/fvp_baser_aemv8r/           @povergoing

boards/arm64/imx8mp_evk/CMakeLists.txt

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/arm64/imx8mp_evk/Kconfig.board

@@ -0,0 +1,7 @@
+# Copyright 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_IMX8MP_EVK_A53
+	bool "NXP i.MX8M Plus EVK A53"
+	depends on SOC_SERIES_IMX8M_A53
+	select ARM64

boards/arm64/imx8mp_evk/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_IMX8MP_EVK_A53
+
+config BOARD
+	default "imx8mp_evk"
+
+endif # BOARD_IMX8MP_EVK_A53

boards/arm64/imx8mp_evk/board.cmake

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/arm64/imx8mp_evk/doc/index.rst

@@ -0,0 +1,127 @@
+.. _imx8mp_evk:
+
+NXP i.MX8MP EVK (Cortex-A53)
+#################################
+
+Overview
+********
+
+i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications
+processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
+Zephyr OS is ported to run on the Cortex®-A53 core.
+
+- Board features:
+
+  - RAM: 2GB LPDDR4
+  - Storage:
+
+    - SanDisk 16GB eMMC5.1
+    - Micron 32MB QSPI NOR
+    - microSD Socket
+  - Wireless:
+
+    - WiFi: 2.4/5GHz IEEE 802.11b/g/n
+    - Bluetooth: v4.1
+  - USB:
+
+    - OTG - 2x type C
+  - Ethernet
+  - PCI-E M.2
+  - Connectors:
+
+    - 40-Pin Dual Row Header
+  - LEDs:
+
+    - 1x Power status LED
+    - 1x UART LED
+  - Debug
+
+    - JTAG 20-pin connector
+    - MicroUSB for UART debug, two COM ports for A53 and M4
+
+More information about the board can be found at the
+`NXP website`_.
+
+Supported Features
+==================
+
+The Zephyr mimx8mm_evk_a53 board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| GIC-v3    | on-chip    | interrupt controller                |
++-----------+------------+-------------------------------------+
+| ARM TIMER | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 8 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART2.
+
+Programming and Debugging
+*************************
+
+Use U-Boot to load and kick zephyr.bin:
+
+.. code-block:: console
+
+    dhcp 0x93c00000 zephyr.elf; dcache flush; icache flush; dcache off; icache off; bootelf zephyr.elf
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: imx8mp_evk
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it and
+display the following console output:
+
+.. code-block:: console
+
+      ## Starting application at 0xc0001074 ...
+    *** Booting Zephyr OS build v2.6.0-rc3-8-gf689d5e7c216  ***
+    Secondary CPU core 1 (MPID:0x1) is up
+    thread_a: Hello World from cpu 0 on imx8mp_evk!
+    thread_b: Hello World from cpu 1 on imx8mp_evk!
+    thread_a: Hello World from cpu 0 on imx8mp_evk!
+    thread_b: Hello World from cpu 1 on imx8mp_evk!
+    thread_a: Hello World from cpu 0 on imx8mp_evk!
+    thread_b: Hello World from cpu 1 on imx8mp_evk!
+    thread_a: Hello World from cpu 0 on imx8mp_evk!
+    thread_b: Hello World from cpu 1 on imx8mp_evk!
+    thread_a: Hello World from cpu 0 on imx8mp_evk!
+    thread_b: Hello World from cpu 1 on imx8mp_evk!
+
+Use Jailhouse hypervisor, after root cell linux is up:
+
+.. code-block:: console
+
+    #jailhouse enable imx8mp.cell
+    #jailhouse cell create imx8mp-zephyr.cell
+    #jailhouse cell load 1 zephyr.bin -a 0xc0000000
+    #jailhouse cell start 1
+
+References
+==========
+
+.. _NXP website:
+   https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
+
+.. _i.MX 8M Applications Processor Reference Manual:
+   https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf

boards/arm64/imx8mp_evk/imx8mp_evk.dts

@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8mp_a53.dtsi>
+
+/ {
+	model = "NXP i.MX8MP A53";
+	compatible = "fsl,imx8mp";
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+		label = "PSCI";
+	};
+
+	uartclk: apb-pclk {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(24)>;
+		#clock-cells = <0>;
+		status = "okay";
+	};
+
+	sram0: memory@40000000 {
+		reg = <0x40000000 DT_SIZE_M(128)>;
+	};
+};
+
+&uart2 {
+	clocks = <&uartclk>;
+	status = "okay";
+	current-speed = <115200>;
+};
+
+&uart4 {
+	clocks = <&uartclk>;
+};

boards/arm64/imx8mp_evk/imx8mp_evk.yaml

@@ -0,0 +1,12 @@
+identifier: imx8mp_evk
+name: NXP i.MX8M Plus EVK A53
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram:  128
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/imx8mp_evk/imx8mp_evk_defconfig

@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_IMX8M_A53=y
+CONFIG_SOC_MIMX8MP_A53=y
+CONFIG_BOARD_IMX8MP_EVK_A53=y
+CONFIG_ARM_ARCH_TIMER=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_PA_BITS_48=y
+
+# Serial Drivers
+CONFIG_SERIAL=n
+CONFIG_UART_INTERRUPT_DRIVEN=n
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=n
+
+CONFIG_RAM_CONSOLE=y
+CONFIG_RAM_CONSOLE_BUFFER_SIZE=2048
+
+CONFIG_ARMV8_A_NS=y
+CONFIG_DYNAMIC_INTERRUPTS=y
+CONFIG_TIMEOUT_64BIT=y
+
+CONFIG_CLOCK_CONTROL=n
+
+# SMP support
+CONFIG_SMP=y
+CONFIG_MP_NUM_CPUS=2
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARMV8_A_NS=y
+
+# PSCI is supported
+CONFIG_PM_CPU_OPS=y
+CONFIG_PM_CPU_OPS_PSCI=y

boards/arm64/imx8mp_evk/imx8mp_evk_jailhouse.dts

@@ -0,0 +1,43 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8mp_a53.dtsi>
+
+/ {
+	model = "NXP i.MX8MP A53";
+	compatible = "fsl,imx8mp";
+
+	chosen {
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+		zephyr,sram = &sram0;
+	};
+
+	uartclk: apb-pclk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+		label = "PSCI";
+	};
+
+	sram0: memory@c0000000 {
+		reg = <0xc0000000 DT_SIZE_M(128)>;
+	};
+
+};
+
+&uart4 {
+	status = "okay";
+	clocks = <&uartclk>;
+	current-speed = <115200>;
+};

boards/arm64/imx8mp_evk/imx8mp_evk_jailhouse.yaml

@@ -0,0 +1,12 @@
+identifier: imx8mp_evk_jailhouse
+name: NXP i.MX8M Plus EVK A53 Jailhouse Inmate Cell
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram:  128
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/imx8mp_evk/imx8mp_evk_jailhouse_defconfig

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_IMX8M_A53=y
+CONFIG_SOC_MIMX8MP_A53=y
+CONFIG_BOARD_IMX8MP_EVK_A53=y
+CONFIG_ARM_ARCH_TIMER=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_PA_BITS_48=y
+
+# Serial Drivers
+CONFIG_SERIAL=n
+CONFIG_UART_INTERRUPT_DRIVEN=n
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=n
+
+CONFIG_JAILHOUSE_DEBUG_CONSOLE=y
+
+CONFIG_ARMV8_A_NS=y
+CONFIG_DYNAMIC_INTERRUPTS=y
+CONFIG_TIMEOUT_64BIT=y
+
+CONFIG_CLOCK_CONTROL=n
+
+# SMP support
+CONFIG_SMP=y
+CONFIG_MP_NUM_CPUS=2
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARMV8_A_NS=y
+
+# PSCI is supported
+CONFIG_PM_CPU_OPS=y
+CONFIG_PM_CPU_OPS_PSCI=y

dts/arm64/nxp/nxp_imx8mp_a53.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm64/armv8-a.dtsi>
+#include <dt-bindings/clock/imx_ccm.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,sram = &sram0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <1>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		label = "arch_timer";
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@38800000 {
+		compatible = "arm,gic";
+		reg = <0x38800000 0x10000>, /* GIC Dist */
+		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		label = "GIC";
+		status = "okay";
+	};
+
+	soc {
+		ana_pll: ana_pll@30360000 {
+			compatible = "nxp,imx-ana";
+			reg = <0x30360000 DT_SIZE_K(64)>;
+			label = "ANA_PLL";
+		};
+
+		ccm: ccm@30380000 {
+			compatible = "nxp,imx-ccm";
+			reg = <0x30380000 DT_SIZE_K(64)>;
+			label = "CCM";
+			#clock-cells = <3>;
+		};
+
+		uart2: uart@30890000 {
+			compatible = "nxp,imx-iuart";
+			reg = <0x30890000 DT_SIZE_K(64)>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL 0>;
+			interrupt-names = "irq_0";
+			interrupt-parent = <&gic>;
+			label = "UART_2";
+			status = "disabled";
+		};
+
+		uart4: uart@30a60000 {
+			compatible = "nxp,imx-iuart";
+			reg = <0x30a60000 DT_SIZE_K(64)>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL 0>;
+			interrupt-names = "irq_0";
+			interrupt-parent = <&gic>;
+			label = "UART_4";
+			status = "disabled";
+		};
+	};
+};

soc/arm64/nxp_imx/imx8m/Kconfig.defconfig.imx8mp

@@ -0,0 +1,26 @@
+# Copyright 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX8MP_A53
+
+config SOC
+	default "imx8mp"
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config NUM_IRQS
+	int
+	default 240
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 8000000
+
+endif

soc/arm64/nxp_imx/imx8m/Kconfig.soc

@@ -14,6 +14,15 @@ config SOC_IMX8MM_A53
 	select HAS_MCUX if CLOCK_CONTROL
 	select HAS_MCUX_CCM if CLOCK_CONTROL
 
+config SOC_MIMX8MP_A53
+	bool "NXP i.MX8MP A53"
+	select ARM64
+	select CPU_CORTEX_A53
+	select ARM_ARCH_TIMER
+	select GIC_V3
+	select HAS_MCUX if CLOCK_CONTROL
+	select HAS_MCUX_CCM if CLOCK_CONTROL
+
 endchoice
 
 if SOC_IMX8MM_A53