6b57b3b786
Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
31 lines
581 B
C
31 lines
581 B
C
/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief UART cases header file
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*
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* Header file for UART cases
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*/
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#ifndef __TEST_UART_H__
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#define __TEST_UART_H__
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#include <zephyr/drivers/uart.h>
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#include <zephyr/ztest.h>
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/* RX and TX pins have to be connected together*/
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#if DT_NODE_EXISTS(DT_NODELABEL(dut))
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#define UART_NODE DT_NODELABEL(dut)
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#elif defined(CONFIG_SOC_SERIES_ESP32C3)
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#define UART_NODE DT_NODELABEL(uart1)
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#else
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#define UART_NODE DT_CHOSEN(zephyr_console)
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#endif
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#endif /* __TEST_UART_H__ */
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