Ruibin Chang 0c3bb75a05 ITE soc/riscv/riscv-ite/common/chipregs: add registers and IRQ num ... Add registers and IRQ number for PD control. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>		2021-06-17 12:42:19 +02:00
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arm-gic.h	interrupt_controller: gic: update default priority	2020-07-01 08:02:57 -04:00
intel-ioapic.h	dts: x86: configure different IO APIC delivery modes for various devices	2020-05-08 22:32:39 -04:00
ite-intc.h	ITE soc/riscv/riscv-ite/common/chipregs: add registers and IRQ num	2021-06-17 12:42:19 +02:00
openisa-intmux.h