Daniel Leung 0d7bdbc876 xtensa: use highest available EPC/EPS regs in restore context ... There may be Xtensa SoCs which don't have high enough interrupt levels for EPC6/EPS6 to exist in _restore_context. So changes these to those which should be available according to the ISA config file. Fixes #30126 Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2021-01-05 10:31:45 -08:00
..
offsets	headers: Refactor kernel and arch headers.	2019-11-06 16:07:32 -08:00
startup	Revert "arch: xtensa: Use reset-vector.S in booloader code"	2020-02-08 10:01:24 +02:00
atomic.S	kernel: add APIs for atomic os on pointers	2020-03-10 10:18:16 -04:00
CMakeLists.txt	xtensa: add support for thread local storage	2020-10-24 10:52:00 -07:00
cpu_idle.c	tracing: move headers under include/tracing	2020-02-07 15:58:05 -05:00
crt1.S	arch/xtensa: Don't clear BSS on MP startup when !SMP	2020-10-21 06:38:53 -04:00
fatal.c	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
irq_manage.c	arch: Apply dynamic IRQ API change	2020-09-02 13:48:13 +02:00
irq_offload.c	isr: Normalize usage of device instance through ISR	2020-09-02 13:48:13 +02:00
tls.c	xtensa: add support for thread local storage	2020-10-24 10:52:00 -07:00
window_vectors.S	headers: Refactor kernel and arch headers.	2019-11-06 16:07:32 -08:00
xtensa_intgen.py	xtensa: xtensa_intgen.py: Change 'not lvl in ...' to 'lvl not in ...'	2019-09-07 07:55:01 -04:00
xtensa_intgen.tmpl
xtensa-asm2-util.S	xtensa: use highest available EPC/EPS regs in restore context	2021-01-05 10:31:45 -08:00
xtensa-asm2.c	xtensa: use highest available EPC/EPS regs in restore context	2021-01-05 10:31:45 -08:00