398d9e3d49
Adds support for the primary m4 core to configure the boot address and start the clock for the secondary risc-v core. Unlike the msdk which defers this function to applications and requires users to copy/paste code from an msdk example application into their own application, in zephyr it is implemented in the common soc init routine of the primary core. It can be enabled/disabled and configured with Kconfig symbols and a devicetree chosen node, allowing applications to override board-level defaults if desired using overlays instead of modifying zephyr code. Signed-off-by: Maureen Helm <maureen.helm@analog.com>
45 lines
939 B
C
45 lines
939 B
C
/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for MAX32xxx MCUs
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <wrap_max32_sys.h>
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#ifdef CONFIG_MAX32_SECONDARY_RV32
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#include <fcr_regs.h>
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#endif
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#if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
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bool z_arm_on_enter_cpu_idle(void)
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{
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/* Returning false prevent device goes to sleep mode */
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return false;
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}
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#endif
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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/* Apply device related preinit configuration */
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max32xx_system_init();
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#ifdef CONFIG_MAX32_SECONDARY_RV32
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MXC_FCR->urvbootaddr = CONFIG_MAX32_SECONDARY_RV32_BOOT_ADDRESS;
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MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CPU1);
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MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1;
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#endif /* CONFIG_MAX32_SECONDARY_RV32 */
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}
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