Laurentiu Mihalcea 1f483b37ea drivers: clock_control: mcux_ccm: support QM/QXP's ESAI/AUD_PLL1 clocks ... Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>		2025-06-24 09:13:45 +02:00
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nxp_imx8.dtsi	drivers: clock_control: mcux_ccm: support QM/QXP's ESAI/AUD_PLL1 clocks	2025-06-24 09:13:45 +02:00
nxp_imx8m.dtsi
nxp_imx8qm.dtsi
nxp_imx8qxp.dtsi
nxp_imx8ulp.dtsi	dts: xtensa: nxp: add mailbox node	2025-04-07 15:17:34 +02:00
nxp_imxrt700_hifi1.dtsi	dts: xtensa: nxp: Add device tree for HiFi1 core from NXP i.MXRT700	2025-03-07 19:42:36 +01:00
nxp_imxrt700_hifi4.dtsi
nxp_rt685_hifi4.dtsi	dts: xtensa: Add DT for SoC mimxrt685s/hifi4	2025-05-21 20:11:19 +02:00