abeccfec28
This change add support for using more than 32 interrupts. Signed-off-by: William Tambe <williamt@cadence.com>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/irq_offload.h>
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#include <zephyr/zsr.h>
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#include <zephyr/irq.h>
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static struct {
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irq_offload_routine_t fn;
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const void *arg;
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} offload_params[CONFIG_MP_MAX_NUM_CPUS];
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static void irq_offload_isr(const void *param)
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{
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ARG_UNUSED(param);
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uint8_t cpu_id = _current_cpu->id;
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offload_params[cpu_id].fn(offload_params[cpu_id].arg);
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}
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void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
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{
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IRQ_CONNECT(ZSR_IRQ_OFFLOAD_INT, 0, irq_offload_isr, NULL, 0);
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unsigned int intenable, key = arch_irq_lock();
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uint8_t cpu_id = _current_cpu->id;
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offload_params[cpu_id].fn = routine;
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offload_params[cpu_id].arg = parameter;
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#if XCHAL_NUM_INTERRUPTS > 32
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switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) {
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case 0:
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__asm__ volatile("rsr.intenable %0" : "=r"(intenable));
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break;
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case 1:
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__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable));
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break;
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#if XCHAL_NUM_INTERRUPTS > 64
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case 2:
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__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable));
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break;
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#endif
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#if XCHAL_NUM_INTERRUPTS > 96
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case 3:
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__asm__ volatile("rsr.intenable3 %0" : "=r"(intenable));
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break;
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#endif
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default:
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break;
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}
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#else
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__asm__ volatile("rsr.intenable %0" : "=r"(intenable));
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#endif
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intenable |= BIT((ZSR_IRQ_OFFLOAD_INT & 31U));
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#if XCHAL_NUM_INTERRUPTS > 32
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switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) {
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case 0:
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__asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync"
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:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
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break;
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case 1:
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__asm__ volatile("wsr.intenable1 %0; wsr.intset1 %0; rsync"
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:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
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break;
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#if XCHAL_NUM_INTERRUPTS > 64
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case 2:
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__asm__ volatile("wsr.intenable2 %0; wsr.intset2 %0; rsync"
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:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
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break;
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#endif
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#if XCHAL_NUM_INTERRUPTS > 96
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case 3:
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__asm__ volatile("wsr.intenable3 %0; wsr.intset3 %0; rsync"
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:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
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break;
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#endif
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default:
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break;
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}
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#else
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__asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync"
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:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
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#endif
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arch_irq_unlock(key);
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}
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void arch_irq_offload_init(void)
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{
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}
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