zephyr/arch/xtensa/core
Daniel Leung a9574c17ae xtensa: gdbstub: fix code stepping
The ICOUNTLEVEL register needs to be manipulated carefully
according to where we want to stop.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-06-30 15:19:59 -05:00
..
offsets xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
startup xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00
CMakeLists.txt arch: xtensa: Add semihosting support 2025-06-19 09:36:42 +02:00
coredump.c xtensa: coredump: support dumping privilege stack 2024-09-21 11:29:39 +02:00
cpu_idle.c
crt1.S
debug_helpers_asm.S
elf.c llext: make unresolved symbol errors fatal 2025-06-17 16:09:50 +02:00
fatal.c Revert "arch: deprecate _current" 2025-01-10 07:49:08 +01:00
gdbstub.c xtensa: gdbstub: fix code stepping 2025-06-30 15:19:59 -05:00
gen_vectors.py
gen_zsr.py xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
irq_manage.c xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00
irq_offload.c xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00
mem_manage.c
mmu.c xtensa: userspace: pre-compute MMU registers at domain init 2025-04-17 00:57:19 +02:00
mpu.c arch: tweak xtensa_mem_kernel_has_access() API 2025-06-19 00:03:00 +02:00
prep_c.c xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
ptables.c arch: tweak xtensa_mem_kernel_has_access() API 2025-06-19 00:03:00 +02:00
README_MMU.txt
README_WINDOWS.rst
semihost.c arch: xtensa: Add semihosting support 2025-06-19 09:36:42 +02:00
smp.c
syscall_helper.c arch: xtensa: Update arch_user_string_nlen() 2025-06-19 00:03:00 +02:00
thread.c xtensa: userspace: prevent potential privilege escalation 2025-04-17 00:57:19 +02:00
timing.c
tls.c
userspace.S xtensa: allow flushing auto-refill DTLBs on page table swap 2025-05-28 20:01:58 +02:00
vector_handlers.c xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00
window_vectors.S
xcc_stubs.c
xtensa_asm2_util.S xtensa: allow flushing auto-refill DTLBs on page table swap 2025-05-28 20:01:58 +02:00
xtensa_backtrace.c
xtensa_hifi.S
xtensa_intgen.py xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00
xtensa_intgen.tmpl xtensa: support for more than 32 interrupts 2025-06-27 08:59:56 -10:00