Yanir Levin 6df14b432e arc: cache: Support region operations, SLC, and entire cache operations ... Added configurable support for L1 cache region operations, which offers improved performance over line operations. Added configurable support for SLC (system level cache). Added support for entire cache operations: flush_all, invd_all, flush_and_invd_all. Reviewed-by: Aaron Komisar <aaron.komisar@tandemg.com> Signed-off-by: Yanir Levin <ylevin@gsitechnology.com>		2025-07-19 09:42:20 +02:00
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arc	arc: cache: Support region operations, SLC, and entire cache operations	2025-07-19 09:42:20 +02:00
arm	arch: arm: core: cortex_a_r: mark unused function argument	2025-07-09 00:26:17 -05:00
arm64	arch: arm64: core: fpu: mark unused function argument	2025-07-11 08:18:43 -10:00
common	arch: common: update RISC-V semihosting spec link	2025-07-01 10:15:32 -05:00
mips	arch/common: Mark interrupt tables const when !DYNAMIC_INTERRUPTS	2025-06-10 22:13:09 +02:00
posix	arch/posix: Remove support for CONFIG_NATIVE_APPLICATION	2025-07-19 09:38:15 +02:00
riscv	kconfig: fix typo in (arch, boards, kernel, modules, samples, share)	2025-07-01 10:58:54 -10:00
rx	include: arch: rx: Change data symbol name	2025-06-26 14:07:03 +02:00
sparc
x86	x86: rename DEBUG_INFO to X86_DEBUG_INFO	2025-06-20 14:43:42 -05:00
xtensa	xtensa: tracing: instrument thread switching	2025-07-08 18:34:11 -05:00
archs.yml	scripts: hwm_v2: add full_name property for archs	2025-06-06 10:29:44 +02:00
CMakeLists.txt
Kconfig	riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A	2025-06-30 15:17:47 -05:00