arc: cache: Support region operations, SLC, and entire cache operations
Added configurable support for L1 cache region operations, which offers improved performance over line operations. Added configurable support for SLC (system level cache). Added support for entire cache operations: flush_all, invd_all, flush_and_invd_all. Reviewed-by: Aaron Komisar <aaron.komisar@tandemg.com> Signed-off-by: Yanir Levin <ylevin@gsitechnology.com>
This commit is contained in:
Yanir Levin
Alberto Escolar
parent
dcd9adec29
commit
6df14b432e
@ -370,6 +370,28 @@ endmenu
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config DCACHE_LINE_SIZE
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default 32
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config ARC_DCACHE_REGION_OPERATIONS
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bool "DCACHE region operations"
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depends on CACHE_MANAGEMENT && DCACHE
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default n
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help
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Perform L1 data cache management operations by regions rather than line by line in a loop,
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improves performance of cache management operations.
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config ARC_SLC
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bool "System level cache"
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depends on CACHE_MANAGEMENT && DCACHE && (CPU_HS4X || CPU_HS3X)
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default n
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help
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This option enables System Level Cache, and adds SLC support to the data cache management operations.
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config ARC_SLC_LINE_SIZE
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int "SLC line size"
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depends on ARC_SLC
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default 128
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help
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Size in bytes of a CPU system level cache line.
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config ARC_EXCEPTION_STACK_SIZE
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int "ARC exception handling stack size"
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default 768 if !64BIT
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@ -2,6 +2,7 @@
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/*
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* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
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* Copyright (c) 2025 GSI Technology, All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -29,16 +30,34 @@
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size_t sys_cache_line_size;
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#endif
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#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */
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#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */
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#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */
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#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */
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#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */
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#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */
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#define DC_CTRL_FLUSH_STATUS 0x100/* flush status */
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#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */
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#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */
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#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */
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#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */
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#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */
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#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */
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#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */
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#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */
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#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */
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#define DC_CTRL_FLUSH_STATUS 0x100 /* flush status */
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#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */
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#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */
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#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */
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#define DC_CTRL_INVALIDATE_MODE 0x40 /* d-cache invalidate mode bit */
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#define DC_CTRL_REGION_OP 0xe00 /* d-cache region operation */
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#define MMU_BUILD_PHYSICAL_ADDR_EXTENSION 0x1000 /* physical address extension enable mask */
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#define SLC_CTRL_DISABLE 0x1 /* SLC disable */
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#define SLC_CTRL_INVALIDATE_MODE 0x40 /* SLC invalidate mode */
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#define SLC_CTRL_BUSY_STATUS 0x100 /* SLC busy status */
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#define SLC_CTRL_REGION_OP 0xe00 /* SLC region operation */
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#if defined(CONFIG_ARC_SLC)
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/*
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* spinlock is used for SLC access because depending on HW configuration, the SLC might be shared
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* between the cores, and in this case, only one core is allowed to access the SLC register
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* interface at a time.
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*/
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static struct k_spinlock slc_lock;
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#endif
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static bool dcache_available(void)
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{
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@ -55,9 +74,189 @@ static void dcache_dc_ctrl(uint32_t dcache_en_mask)
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}
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}
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static bool pae_exists(void)
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{
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uint32_t bcr = z_arc_v2_aux_reg_read(_ARC_V2_MMU_BUILD);
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return 1 == FIELD_GET(MMU_BUILD_PHYSICAL_ADDR_EXTENSION, bcr);
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}
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#if defined(CONFIG_ARC_SLC)
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static void slc_enable(void)
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{
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uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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val &= ~SLC_CTRL_DISABLE;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, val);
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}
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static void slc_high_addr_init(void)
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{
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END1, 0);
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START1, 0);
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}
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static void slc_flush_region(void *start_addr_ptr, size_t size)
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{
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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K_SPINLOCK(&slc_lock) {
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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ctrl &= ~SLC_CTRL_REGION_OP;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl);
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/*
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* END needs to be setup before START (latter triggers the operation)
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* END can't be same as START, so add (l2_line_sz - 1) to sz
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*/
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end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr);
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/* Align start address to cache line size, see STAR 5103816 */
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START,
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start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1));
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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static void slc_invalidate_region(void *start_addr_ptr, size_t size)
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{
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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K_SPINLOCK(&slc_lock) {
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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ctrl &= ~SLC_CTRL_INVALIDATE_MODE;
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ctrl &= ~SLC_CTRL_REGION_OP;
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ctrl |= FIELD_PREP(SLC_CTRL_REGION_OP, 0x1);
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl);
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/*
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* END needs to be setup before START (latter triggers the operation)
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* END can't be same as START, so add (l2_line_sz - 1) to sz
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*/
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end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr);
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/* Align start address to cache line size, see STAR 5103816 */
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START,
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start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1));
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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static void slc_flush_and_invalidate_region(void *start_addr_ptr, size_t size)
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{
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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K_SPINLOCK(&slc_lock) {
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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ctrl |= SLC_CTRL_INVALIDATE_MODE;
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ctrl &= ~SLC_CTRL_REGION_OP;
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ctrl |= FIELD_PREP(SLC_CTRL_REGION_OP, 0x1);
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl);
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/*
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* END needs to be setup before START (latter triggers the operation)
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* END can't be same as START, so add (l2_line_sz - 1) to sz
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*/
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end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr);
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/* Align start address to cache line size, see STAR 5103816 */
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START,
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start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1));
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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static void slc_flush_all(void)
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{
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K_SPINLOCK(&slc_lock) {
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_FLUSH, 0x1);
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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static void slc_invalidate_all(void)
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{
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uint32_t ctrl;
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K_SPINLOCK(&slc_lock) {
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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ctrl &= ~SLC_CTRL_INVALIDATE_MODE;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl);
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_INVALIDATE, 0x1);
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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static void slc_flush_and_invalidate_all(void)
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{
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uint32_t ctrl;
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K_SPINLOCK(&slc_lock) {
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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ctrl |= SLC_CTRL_INVALIDATE_MODE;
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl);
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z_arc_v2_aux_reg_write(_ARC_V2_SLC_INVALIDATE, 0x1);
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/* Make sure "busy" bit reports correct status, see STAR 9001165532 */
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z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL);
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while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) {
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/* Do Nothing */
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}
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}
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}
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#endif /* CONFIG_ARC_SLC */
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void arch_dcache_enable(void)
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{
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dcache_dc_ctrl(DC_CTRL_DC_ENABLE);
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#if defined(CONFIG_ARC_SLC)
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slc_enable();
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#endif
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}
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void arch_dcache_disable(void)
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@ -65,17 +264,107 @@ void arch_dcache_disable(void)
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/* nothing */
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}
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int arch_dcache_flush_range(void *start_addr_ptr, size_t size)
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#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS)
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static void dcache_high_addr_init(void)
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{
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z_arc_v2_aux_reg_write(_ARC_V2_DC_PTAG_HI, 0);
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}
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static void dcache_flush_region(void *start_addr_ptr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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unsigned int key;
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key = arch_irq_lock(); /* --enter critical section-- */
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
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ctrl &= ~DC_CTRL_REGION_OP;
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z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
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end_addr = start_addr + size + line_size - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr);
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z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr);
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while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) {
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/* Do nothing */
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}
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arch_irq_unlock(key); /* --exit critical section-- */
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}
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static void dcache_invalidate_region(void *start_addr_ptr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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unsigned int key;
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key = arch_irq_lock(); /* --enter critical section-- */
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
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ctrl &= ~DC_CTRL_INVALIDATE_MODE;
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ctrl &= ~DC_CTRL_REGION_OP;
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ctrl |= FIELD_PREP(DC_CTRL_REGION_OP, 0x1);
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z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
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end_addr = start_addr + size + line_size - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr);
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z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr);
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arch_irq_unlock(key); /* --exit critical section-- */
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}
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static void dcache_flush_and_invalidate_region(void *start_addr_ptr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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uint32_t ctrl;
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unsigned int key;
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key = arch_irq_lock(); /* --enter critical section-- */
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
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ctrl |= DC_CTRL_INVALIDATE_MODE;
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ctrl &= ~DC_CTRL_REGION_OP;
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ctrl |= FIELD_PREP(DC_CTRL_REGION_OP, 0x1);
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z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
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end_addr = start_addr + size + line_size - 1;
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z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr);
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z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr);
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while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) {
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/* Do nothing */
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}
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arch_irq_unlock(key); /* --exit critical section-- */
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}
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#else /* CONFIG_ARC_DCACHE_REGION_OPERATIONS */
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static void dcache_flush_lines(void *start_addr_ptr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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unsigned int key;
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if (!dcache_available() || (size == 0U) || line_size == 0U) {
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return -ENOTSUP;
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}
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end_addr = start_addr + size;
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start_addr = ROUND_DOWN(start_addr, line_size);
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@ -98,25 +387,25 @@ int arch_dcache_flush_range(void *start_addr_ptr, size_t size)
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} while (start_addr < end_addr);
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arch_irq_unlock(key); /* --exit critical section-- */
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return 0;
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}
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int arch_dcache_invd_range(void *start_addr_ptr, size_t size)
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static void dcache_invalidate_lines(void *start_addr_ptr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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unsigned int key;
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uint32_t ctrl;
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if (!dcache_available() || (size == 0U) || line_size == 0U) {
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return -ENOTSUP;
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}
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end_addr = start_addr + size;
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start_addr = ROUND_DOWN(start_addr, line_size);
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key = arch_irq_lock(); /* -enter critical section- */
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ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
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ctrl &= ~DC_CTRL_INVALIDATE_MODE;
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z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
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do {
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z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDL, start_addr);
|
||||
__builtin_arc_nop();
|
||||
@ -125,28 +414,182 @@ int arch_dcache_invd_range(void *start_addr_ptr, size_t size)
|
||||
start_addr += line_size;
|
||||
} while (start_addr < end_addr);
|
||||
irq_unlock(key); /* -exit critical section- */
|
||||
}
|
||||
|
||||
static void dcache_flush_and_invalidate_lines(void *start_addr_ptr, size_t size)
|
||||
{
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
uintptr_t start_addr = (uintptr_t)start_addr_ptr;
|
||||
uintptr_t end_addr;
|
||||
unsigned int key;
|
||||
uint32_t ctrl;
|
||||
|
||||
end_addr = start_addr + size;
|
||||
start_addr = ROUND_DOWN(start_addr, line_size);
|
||||
|
||||
key = arch_irq_lock(); /* -enter critical section- */
|
||||
|
||||
ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
|
||||
ctrl |= DC_CTRL_INVALIDATE_MODE;
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
|
||||
|
||||
do {
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDL, start_addr);
|
||||
__builtin_arc_nop();
|
||||
__builtin_arc_nop();
|
||||
__builtin_arc_nop();
|
||||
start_addr += line_size;
|
||||
} while (start_addr < end_addr);
|
||||
irq_unlock(key); /* -exit critical section- */
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARC_DCACHE_REGION_OPERATIONS */
|
||||
|
||||
int arch_dcache_flush_range(void *start_addr_ptr, size_t size)
|
||||
{
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
|
||||
if (!dcache_available() || (size == 0U) || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS)
|
||||
dcache_flush_region(start_addr_ptr, size);
|
||||
#else
|
||||
dcache_flush_lines(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_flush_region(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_dcache_invd_range(void *start_addr_ptr, size_t size)
|
||||
{
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
|
||||
if (!dcache_available() || (size == 0U) || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS)
|
||||
dcache_invalidate_region(start_addr_ptr, size);
|
||||
#else
|
||||
dcache_invalidate_lines(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_invalidate_region(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_dcache_flush_and_invd_range(void *start_addr_ptr, size_t size)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
|
||||
if (!dcache_available() || (size == 0U) || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS)
|
||||
dcache_flush_and_invalidate_region(start_addr_ptr, size);
|
||||
#else
|
||||
dcache_flush_and_invalidate_lines(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_flush_and_invalidate_region(start_addr_ptr, size);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_dcache_flush_all(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
unsigned int key;
|
||||
|
||||
if (!dcache_available() || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_FLSH, 0x1);
|
||||
|
||||
while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_flush_all();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_dcache_invd_all(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
unsigned int key;
|
||||
uint32_t ctrl;
|
||||
|
||||
if (!dcache_available() || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
|
||||
ctrl &= ~DC_CTRL_INVALIDATE_MODE;
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
|
||||
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 0x1);
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_invalidate_all();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_dcache_flush_and_invd_all(void)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
size_t line_size = sys_cache_data_line_size_get();
|
||||
unsigned int key;
|
||||
uint32_t ctrl;
|
||||
|
||||
if (!dcache_available() || line_size == 0U) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL);
|
||||
ctrl |= DC_CTRL_INVALIDATE_MODE;
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl);
|
||||
|
||||
z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 0x1);
|
||||
|
||||
while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) {
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_flush_and_invalidate_all();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
|
||||
@ -224,6 +667,19 @@ static int init_dcache(void)
|
||||
init_dcache_line_size();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init high address registers to 0 if PAE exists, cache operations for 40 bit addresses not
|
||||
* implemented
|
||||
*/
|
||||
if (pae_exists()) {
|
||||
#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS)
|
||||
dcache_high_addr_init();
|
||||
#endif
|
||||
#if defined(CONFIG_ARC_SLC)
|
||||
slc_high_addr_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -45,6 +45,9 @@
|
||||
#define _ARC_V2_DC_IVDL 0x04a
|
||||
#define _ARC_V2_DC_FLSH 0x04b
|
||||
#define _ARC_V2_DC_FLDL 0x04c
|
||||
#define _ARC_V2_DC_STARTR 0x04d
|
||||
#define _ARC_V2_DC_ENDR 0x04e
|
||||
#define _ARC_V2_DC_PTAG_HI 0x05f
|
||||
#define _ARC_V2_EA_BUILD 0x065
|
||||
#define _ARC_V2_VECBASE_AC_BUILD 0x068
|
||||
#define _ARC_V2_FP_BUILD 0x06b
|
||||
@ -175,6 +178,14 @@
|
||||
#define _ARC_V2_AGU_MOD21 0x5f5
|
||||
#define _ARC_V2_AGU_MOD22 0x5f6
|
||||
#define _ARC_V2_AGU_MOD23 0x5f7
|
||||
#define _ARC_V2_SLC_CTRL 0x903
|
||||
#define _ARC_V2_SLC_FLUSH 0x904
|
||||
#define _ARC_V2_SLC_INVALIDATE 0x905
|
||||
#define _ARC_V2_SLC_RGN_START 0x914
|
||||
#define _ARC_V2_SLC_RGN_START1 0x915
|
||||
#define _ARC_V2_SLC_RGN_END 0x916
|
||||
#define _ARC_V2_SLC_RGN_END1 0x917
|
||||
#define _ARC_V2_SLC_BUILD 0xCE
|
||||
#define _ARC_HW_PF_BUILD 0xf70
|
||||
#define _ARC_HW_PF_CTRL 0x4f
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user