d49cc8a56f
This serves two main purposes: - change the CPU clock via devicetree nodes - provide the APB frequency to device drivers via the clock driver interface Theoretically this could also support choosing between the available clock sources, but right now we only support LPOSC0 going into PLL0, going into AHB. Turning the PLL back off is also not supported since the only current use case is to set the PLL frequency, turn it on, and switch the AHB over to it. Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* Copyright (c) 2024 GARDENA GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_si32_pll
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <SI32_CLKCTRL_A_Type.h>
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#include <SI32_PLL_A_Type.h>
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#include <si32_device.h>
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#define LOG_LEVEL LOG_LEVEL_DBG
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(pll);
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struct clock_control_si32_pll_config {
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SI32_PLL_A_Type *pll;
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};
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struct clock_control_si32_pll_data {
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uint32_t freq;
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};
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static int clock_control_si32_pll_on(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct clock_control_si32_pll_config *config = dev->config;
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struct clock_control_si32_pll_data *data = dev->data;
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if (data->freq == 0) {
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return -ENOTSUP;
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}
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uint32_t dco_range;
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if (data->freq > 80000000) {
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dco_range = 4;
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} else if (data->freq > 76500000) {
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dco_range = 4;
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} else if (data->freq > 62000000) {
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dco_range = 3;
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} else if (data->freq > 49500000) {
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dco_range = 2;
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} else if (data->freq > 35000000) {
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dco_range = 1;
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} else if (data->freq > 23000000) {
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dco_range = 0;
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} else {
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return -ENOTSUP;
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}
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/* lposc0div */
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const uint32_t source_clock_freq = 2500000;
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const uint32_t div_m = 100;
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const uint32_t div_n = (data->freq / source_clock_freq) * (div_m + 1) - 1;
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if (div_n < 32 || div_n > 4095) {
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return -ENOTSUP;
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}
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/* Setup PLL to lock to requested frequency */
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SI32_PLL_A_initialize(config->pll, 0x00, 0x00, 0x00, 0x000FFF0);
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SI32_PLL_A_set_numerator(config->pll, div_n);
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SI32_PLL_A_set_denominator(config->pll, div_m);
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/* TODO: support other clock sources */
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SI32_PLL_A_select_reference_clock_source_lp0oscdiv(config->pll);
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/* Wait for lock */
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SI32_PLL_A_select_disable_dco_output(config->pll);
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SI32_PLL_A_set_frequency_adjuster_value(config->pll, 0xFFF);
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SI32_PLL_A_set_output_frequency_range(config->pll, dco_range);
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/* Lock and block for result */
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SI32_PLL_A_select_dco_frequency_lock_mode(config->pll);
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while (!(SI32_PLL_A_is_locked(config->pll) ||
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SI32_PLL_A_is_saturation_low_interrupt_pending(config->pll) ||
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SI32_PLL_A_is_saturation_high_interrupt_pending(config->pll)))
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;
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return 0;
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}
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static int clock_control_si32_pll_off(const struct device *dev, clock_control_subsys_t sys)
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{
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return -ENOTSUP;
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}
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static int clock_control_si32_pll_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct clock_control_si32_pll_data *data = dev->data;
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*rate = data->freq;
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return 0;
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}
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static int clock_control_si32_pll_set_rate(const struct device *dev, clock_control_subsys_t sys,
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clock_control_subsys_rate_t rate_)
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{
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struct clock_control_si32_pll_data *data = dev->data;
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const uint32_t *rate = rate_;
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data->freq = *rate;
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return 0;
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}
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static struct clock_control_driver_api clock_control_si32_pll_api = {
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.on = clock_control_si32_pll_on,
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.off = clock_control_si32_pll_off,
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.get_rate = clock_control_si32_pll_get_rate,
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.set_rate = clock_control_si32_pll_set_rate,
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};
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static int clock_control_si32_pll_init(const struct device *dev)
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{
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SI32_CLKCTRL_A_enable_apb_to_modules_0(SI32_CLKCTRL_0, SI32_CLKCTRL_A_APBCLKG0_PLL0);
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return 0;
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}
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static const struct clock_control_si32_pll_config config = {
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.pll = (SI32_PLL_A_Type *)DT_REG_ADDR(DT_NODELABEL(pll0)),
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};
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static struct clock_control_si32_pll_data data = {
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.freq = 0,
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};
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DEVICE_DT_INST_DEFINE(0, clock_control_si32_pll_init, NULL, &data, &config, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_si32_pll_api);
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