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zephyr/arch/xtensa/core
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Flavio Ceolin 6c6495bb43 xtensa: mmu: Fix rasid initial value 
RASID must not use 0 for any slot. According with documentation:

"""The operation of the processor is undefined if any two of the
four ASIDs are equal or if it contains an ASID of zero"""

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-03-14 13:24:41 -05:00
..
offsets arch: xtensa: Add space for HiFi registers 2024-03-05 10:57:33 +01:00
startup xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
CMakeLists.txt arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
coredump.c xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
cpu_idle.c arch/xtensa: clean up arch_cpu_idle function 2023-11-20 11:14:41 +01:00
crt1.S xtensa: mmu: Simplify initialization 2023-11-21 15:49:48 +01:00
debug_helpers_asm.S xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
elf.c llext: merge llext_mem and llext_section enums 2023-12-14 19:06:55 +00:00
fatal.c xtensa: remove ARG_UNUSED from arch_syscall_oops 2024-02-01 13:09:53 -06:00
gdbstub.c xtensa: rename z_xtensa_irq to simple xtensa_irq 2023-12-13 09:41:24 +01:00
gen_zsr.py xtensa: only need ZSR_FLUSH if CONFIG_KERNEL_COHERENCE 2024-02-01 13:09:53 -06:00
irq_manage.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
irq_offload.c xtensa: irq: Remove CURR_CPU 2024-02-08 09:05:14 +01:00
mem_manage.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
mmu.c xtensa: mmu: Fix rasid initial value 2024-03-14 13:24:41 -05:00
ptables.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
README_MMU.txt xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
README_WINDOWS.rst xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
smp.c xtensa: move arch_spin_relax into smp.c 2023-12-13 09:41:24 +01:00
syscall_helper.c xtensa: userspace: simplify syscall helper 2023-11-21 15:49:48 +01:00
thread.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
timing.c
tls.c
userspace.S arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
vector_handlers.c xtensa: add support for cores without NMI 2024-02-28 17:35:54 +00:00
window_vectors.S arch/xtensa: Rename "ALLOCA" ZSR to "A0SAVE" 2023-11-21 15:49:48 +01:00
xcc_stubs.c
xtensa_asm2_util.S arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
xtensa_backtrace.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
xtensa_hifi.S arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
xtensa_intgen.py
xtensa_intgen.tmpl