Martin Åberg 152d3e46ad soc/riscv: add the QEMU "RISC-V VirtIO board" ... The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>		2021-01-15 13:06:33 -05:00
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arc	dts: remove incorrect use of mmio-sram compatible	2020-07-28 07:31:01 -05:00
arm	dts: arm: stm32: stm32l1x remove eeprom reg attribute & add eeprom sizes	2021-01-15 12:15:40 -05:00
bindings	drivers: wdt: add watchdog driver support for NPCX7 series.	2021-01-15 11:27:10 -05:00
common
nios2	dts: Fix altera vendor prefix	2020-10-21 12:48:34 -04:00
posix
riscv	soc/riscv: add the QEMU "RISC-V VirtIO board"	2021-01-15 13:06:33 -05:00
sparc	soc: GR716A LEON3FT Microcontroller	2020-11-13 14:53:55 -08:00
x86	soc: x86: Add Elkhart Lake SoC definition	2020-12-12 14:16:23 +02:00
xtensa	cavs_v25: switch over to Tigerlake H configuration	2021-01-11 16:10:23 -05:00
binding-template.yaml	edtlib: Match any parent bus when binding lacks an explicit on-bus	2021-01-07 20:07:12 +02:00
Kconfig	dts/Kconfig: Remove HAS_DTS_I2C	2020-09-18 13:34:44 -05:00