Conor Paxton 13f8d80930 dts: riscv: add all contexts and devices to the plic on mpfs ... Microchip's PolarFire SoC has a total of 9 contexts associated with the Platform Interrupt controller (PLIC). the E51 core has a single context (M Mode), and the application processor U54 cores have two each (M mode and S mode, respectively) While we are at it, there are a total of 186 interrupts, not 187. Signed-off-by: Conor Paxton <conor.paxton@microchip.com>		2023-12-06 17:54:29 +00:00
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arc/synopsys	uart: ns16550: use io-mapped DT property for IO port access	2023-09-26 12:03:04 +02:00
arm	dts: arm: ambiq: Add GPIO instances to Apollo4 Blue Plus SoC	2023-12-06 12:11:30 +00:00
arm64	dts: arm64: intel: intel_socfpga: Adding nodes for watchdog	2023-11-27 20:00:29 +01:00
bindings	input: kbd_matrix: add actual-key-mask support	2023-12-06 09:16:45 +00:00
common
nios2/intel	dts: nios2: intel: nios2-qemu: add jtag interrupt	2023-01-27 14:24:43 -05:00
posix
riscv	dts: riscv: add all contexts and devices to the plic on mpfs	2023-12-06 17:54:29 +00:00
sparc/gaisler	dts/sparc/gaisler: add SoC and board compatible strings	2023-05-02 10:53:27 +02:00
x86/intel	dts: x86: intel: raptor_lake: Added LPSS dma node for UART	2023-11-22 17:31:08 +01:00
xtensa	dts/xtensa/nxp: Add dtsi for imx8ulp	2023-12-04 16:41:00 +00:00
binding-template.yaml
Kconfig	dts: drop HAS_DTS	2023-10-20 12:18:17 -07:00