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dts: riscv: add all contexts and devices to the plic on mpfs

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Microchip's PolarFire SoC has a total of 9 contexts associated with the
Platform Interrupt controller (PLIC). the E51 core has a single context
(M Mode), and the application processor U54 cores have two each (M mode
and S mode, respectively)

While we are at it, there are a total of 186 interrupts, not 187.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This commit is contained in:
Conor Paxton 2023-12-02 18:19:18 +00:00 committed by Fabio Baltieri
parent 3c7f10f8e1
commit 13f8d80930
1 changed files with 5 additions and 2 deletions
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7
dts/riscv/microchip/mpfs.dtsi
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@ -120,10 +120,13 @@
#address-cells = <1>;
interrupt-controller;
interrupts-extended = <&hlic0 11
&hlic1 11>;
&hlic1 11 &hlic1 9
&hlic2 11 &hlic2 9
&hlic3 11 &hlic3 9
&hlic4 11 &hlic4 9>;
reg = <0x0c000000 0x04000000>;
riscv,max-priority = <7>;
riscv,ndev = <187>;
riscv,ndev = <186>;
};
uart0: uart@20000000 {