From 13f8d809300299cb56abf763d289e0b2eec0d4dc Mon Sep 17 00:00:00 2001 From: Conor Paxton Date: Sat, 2 Dec 2023 18:19:18 +0000 Subject: [PATCH] dts: riscv: add all contexts and devices to the plic on mpfs Microchip's PolarFire SoC has a total of 9 contexts associated with the Platform Interrupt controller (PLIC). the E51 core has a single context (M Mode), and the application processor U54 cores have two each (M mode and S mode, respectively) While we are at it, there are a total of 186 interrupts, not 187. Signed-off-by: Conor Paxton --- dts/riscv/microchip/mpfs.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi index 4ed4d45e305..e0d206789db 100644 --- a/dts/riscv/microchip/mpfs.dtsi +++ b/dts/riscv/microchip/mpfs.dtsi @@ -120,10 +120,13 @@ #address-cells = <1>; interrupt-controller; interrupts-extended = <&hlic0 11 - &hlic1 11>; + &hlic1 11 &hlic1 9 + &hlic2 11 &hlic2 9 + &hlic3 11 &hlic3 9 + &hlic4 11 &hlic4 9>; reg = <0x0c000000 0x04000000>; riscv,max-priority = <7>; - riscv,ndev = <187>; + riscv,ndev = <186>; }; uart0: uart@20000000 {