24d4becac2
Zephyr is migrating into hardware where memory ordering is starting to matter. The existing gcc-based defaults have always been specifying __ATOMIC_SEQ_CST, which is safe and correct. And all the arch-specific assembly we have currently are either safe or for platforms where barriers aren't needed. Discussion in #42831 made the case that it would be nice if we were to formally promise this, and require it from future implementations. So let's do that. Fixes: #42831 Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| atomic.rst | ||
| cpu_idle.rst | ||
| cxx_support.rst | ||
| fatal.rst | ||
| float.rst | ||
| interrupts.rst | ||
| polling.rst | ||
| thread_local_storage.rst | ||
| version.rst | ||