zephyr/doc/reference/kernel
Andy Ross 24d4becac2 include/atomics: doc: Clarify memory barrier behavior
Zephyr is migrating into hardware where memory ordering is starting to
matter.  The existing gcc-based defaults have always been specifying
__ATOMIC_SEQ_CST, which is safe and correct.  And all the
arch-specific assembly we have currently are either safe or for
platforms where barriers aren't needed.

Discussion in #42831 made the case that it would be nice if we were to
formally promise this, and require it from future implementations.  So
let's do that.

Fixes: #42831

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-03-09 13:46:06 -05:00
..
data_passing doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
memory doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
other include/atomics: doc: Clarify memory barrier behavior 2022-03-09 13:46:06 -05:00
scheduling doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
smp doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
synchronization doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
threads doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
timing doc: use :kconfig:option: domain role 2022-03-02 09:28:37 +01:00
index.rst doc: events: Add events documention 2021-10-16 06:27:10 -04:00