Daniel Leung a9574c17ae xtensa: gdbstub: fix code stepping ... The ICOUNTLEVEL register needs to be manipulated carefully according to where we want to stop. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2025-06-30 15:19:59 -05:00
..
arc	arch: arc: replace "master"/"slave" terminology with inclusive language	2025-06-23 13:43:36 +02:00
arm	soc: xlnx: zynq7000: remove FPU FMAC support	2025-06-27 09:50:43 -05:00
arm64	arch: arm64: replace "master" terminology with "primary"	2025-06-23 13:43:08 +02:00
common	arch: xtensa: Add semihosting support	2025-06-19 09:36:42 +02:00
mips	arch/common: Mark interrupt tables const when !DYNAMIC_INTERRUPTS	2025-06-10 22:13:09 +02:00
posix	arch/posix: Add comment on empty function	2025-05-13 12:09:30 +02:00
riscv	arch: riscv: core: Add support for CONFIG_ISR_TABLES_LOCAL_DECLARATION	2025-06-10 08:47:51 +02:00
rx	include: arch: rx: Change data symbol name	2025-06-26 14:07:03 +02:00
sparc
x86	x86: rename DEBUG_INFO to X86_DEBUG_INFO	2025-06-20 14:43:42 -05:00
xtensa	xtensa: gdbstub: fix code stepping	2025-06-30 15:19:59 -05:00
archs.yml	scripts: hwm_v2: add full_name property for archs	2025-06-06 10:29:44 +02:00
CMakeLists.txt
Kconfig	riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A	2025-06-30 15:17:47 -05:00