soc: xlnx: zynq7000: remove FPU FMAC support

Floating-Point System ID register (FPSID)        = 0x41033094
AArch32 Media and VFP Feature Register 0 (MVFR0) = 0x10110222
AArch32 Media and VFP Feature Register 0 (MVFR1) =  0x1111111

MVFR1 SIMDFMAC, bits [31:28] = 0; FMAC is not supported

Signed-off-by: Simon Maurer <mail@maurer.systems>

arch/arm/core/Kconfig.vfp

@@ -109,17 +109,16 @@ config VFP_U_DP_D16_FP16_FMAC
 	  fused multiply-accumulate) and floating-point exception trapping with 16
 	  double-word registers.
 
-config VFP_DP_D32_FMAC
+config VFP_DP_D32
 	bool
 	select CPU_HAS_VFP
 	select VFP_FEATURE_SINGLE_PRECISION
 	select VFP_FEATURE_DOUBLE_PRECISION
-	select VFP_FEATURE_FMAC
 	select VFP_FEATURE_REGS_S64_D32
 	help
 	  This option signifies the use of a VFP floating-point coprocessor
 	  that supports single- and double-precision operations
-	  (including fused multiply-accumulate) with 32 double-word registers.
+	  with 32 double-word registers.
 
 config VFP_DP_D32_FP16_FMAC
 	bool

soc/xlnx/zynq7000/xc7zxxx/Kconfig

@@ -11,4 +11,4 @@ config SOC_SERIES_XC7ZXXX
 	select CPU_CORTEX_A9
 	select SYSCON
 	select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
-	select VFP_DP_D32_FMAC
+	select VFP_DP_D32

soc/xlnx/zynq7000/xc7zxxxs/Kconfig

@@ -11,4 +11,4 @@ config SOC_SERIES_XC7ZXXXS
 	select CPU_CORTEX_A9
 	select SYSCON
 	select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
-	select VFP_DP_D32_FMAC
+	select VFP_DP_D32