soc: xlnx: zynq7000: add FPU support
According to its datasheet the Zynq 7000 has a VFPv3 FPU Signed-off-by: Simon Maurer <mail@maurer.systems>
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@ -109,6 +109,18 @@ config VFP_U_DP_D16_FP16_FMAC
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fused multiply-accumulate) and floating-point exception trapping with 16
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double-word registers.
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config VFP_DP_D32_FMAC
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bool
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select CPU_HAS_VFP
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select VFP_FEATURE_SINGLE_PRECISION
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select VFP_FEATURE_DOUBLE_PRECISION
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select VFP_FEATURE_FMAC
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select VFP_FEATURE_REGS_S64_D32
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help
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This option signifies the use of a VFP floating-point coprocessor
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that supports single- and double-precision operations
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(including fused multiply-accumulate) with 32 double-word registers.
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config VFP_DP_D32_FP16_FMAC
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bool
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select CPU_HAS_VFP
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@ -48,6 +48,14 @@ if("${ARCH}" STREQUAL "arm")
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elseif(CONFIG_CPU_AARCH32_CORTEX_A)
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if(CONFIG_CPU_CORTEX_A7)
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set(GCC_M_FPU vfpv4-d16)
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elseif(CONFIG_CPU_CORTEX_A9)
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set(GCC_M_FPU vfpv3)
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if(NOT CONFIG_VFP_FEATURE_REGS_S64_D32)
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set(GCC_M_FPU ${GCC_M_FPU}-d16)
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endif()
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if(CONFIG_VFP_FEATURE_HALF_PRECISION)
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set(GCC_M_FPU ${GCC_M_FPU}-fp16)
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endif()
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endif()
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endif()
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endif()
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@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXX
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select CPU_CORTEX_A9
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select SYSCON
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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select VFP_DP_D32_FMAC
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@ -11,3 +11,4 @@ config SOC_SERIES_XC7ZXXXS
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select CPU_CORTEX_A9
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select SYSCON
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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select VFP_DP_D32_FMAC
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