zephyr/soc/xtensa/sample_controller
Andy Ross c174ade4a1 arch/xtensa: Rework irq_offload: automatic config, SMP-safe
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).

Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-02-21 22:10:03 -05:00
..
include
CMakeLists.txt
Kconfig.defconfig arch/xtensa: Rework irq_offload: automatic config, SMP-safe 2022-02-21 22:10:03 -05:00
Kconfig.soc debug: coredump: add xtensa coredump 2021-12-14 07:40:55 -05:00
linker.ld soc: xtensa/sample_controller: add snippets to linker script 2022-02-10 14:24:50 -05:00