2b0d1ae4d0
Transition nrf54h away from the soc specific gpd (global power domain) driver which mixed power domains, pinctrl and gpio pin retention into a non scalable solution, forcing soc specific logic to bleed into nrf drivers. The new solution uses zephyrs PM_DEVICE based power domains to properly model the hardware layout of device and pin power domains, and moves pin retention logic out of drivers into pinctrl and gpio, which are the components which manage pins (pads). Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no> |
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| .. | ||
| acsip | ||
| adi/max32 | ||
| ambiq | ||
| antmicro | ||
| aspeed | ||
| atmel | ||
| broadcom | ||
| ene | ||
| gd | ||
| infineon | ||
| intel_socfpga_std | ||
| microchip | ||
| nordic | ||
| nuvoton | ||
| nxp | ||
| oct | ||
| olimex | ||
| quicklogic | ||
| rakwireless | ||
| raspberrypi/rpi_pico | ||
| realtek/ec | ||
| renesas | ||
| seeed_studio | ||
| silabs | ||
| st | ||
| ti | ||
| we | ||
| xilinx | ||
| armv6-m.dtsi | ||
| armv7-a.dtsi | ||
| armv7-m.dtsi | ||
| armv7-r.dtsi | ||
| armv8-m.dtsi | ||
| armv8-r.dtsi | ||
| armv8.1-m.dtsi | ||
| cortex_r8_virt.dtsi | ||