Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible for netc driver.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added NETC block control device node to handle block control
initialization in netc block driver.
2. Added "nxp,imx-netc" compatible for netc driver.
3. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Update nxp irtc driver to fix issue in init and alarm function.
2. Update RTC device tree binding to support "share-counter".
3. Update RT700 dtsi to support rtc0 for cpu0 and rtc1 for cpu1.
4. Update readme.
5. Update unit test project conf for RT700.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This files can be used by the 32-bit as well as 64-bit ARM
architectures. Move them into the dts/vendor/ti directory to
make the ISA independant.
All nodes located in the AM64x MAIN domain should have the main_
prefix. This makes it more clear where those pins are actually
located in the chip.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The Raspberry Pi Pico 2 uses a QMI flash controller, which differs from the
SSI controller used in the original Pico. Zephyr already has support for
the SSI controller, but lacked support for QMI.
This change adds the QMI flash controller implementation in the
flash_rpi_pico.c driver file. Additionally, the RP2350 SoC devicetree file
(rp2350.dtsi) has been updated to enable and describe the flash controller
for Pico 2.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
update exti num-lines to depict total number of lines
add clocks entry to exti nodes of certain series
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
The GPIO block instance is based on the instance number during the
device driver initialization. This is not correct as instance numbers
in now way reflect any numbering scheme. Therefore, a DTS property
is introduced so that the block instance numbering is indicated
explicitly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add dts support for the STM32C091 and STM32C092 SoCs,
that are part of the STM32C0 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix interrupt level for acmp0 in the dts for xg21 device.
Only radio interrupts are critical and should have priority 0.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
The Network Coprocessor on SiWx91x owns a large part of the flash. Zephyr
is not expected to access to theses areas.
However, it is still technically possible to access these. In addition, we
prefer the DTS contains a comprehensive and transparent description of the
hardware. So update the DTS with the real partitioning of the SoC.
Reference documentation is available here[1].
[1]: https://www.silabs.com/documents/public/application-notes/
an1416-siwx917-soc-memory-map.pdf
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
With commit d280d89 the gpiof port got moved from file stm32u5.dtsi to
file stm32u5_extra.dtsi. stm32u5_extra.dtsi is not included for
STM32U535/545. In same file stm32u5.dtsi still node wkup-pin@8 references
non-existent port gpiof.
Fixes#93445
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
Add declarations for High-Speed External (HSE) and High-Speed Internal
(HSI) clocks.
These clocks, based on oscillators, can be used to generate the system
clocks.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
According to the datasheet the flash erase timing is
typically 2ms, and max 10ms.
H503: DS14053 Rev 4: section 5.3.10, table 45, t_erase_max=10ms
H562/H563: DS14258 Rev 6: section 5.3.11, table 51, t_erase_max=10ms
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
M4F can use uarts from main domain of AM62. However, interrupts are not
supported.
The common main peripheral dts is kept in dts/venodor/ti to allow
sharing between arm targets (m4, r5) and arm64 targets (a53).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add stm32l1_disco and nucleo_l152re overlays for testing
sleep/stop/standby modes:
- samples/boards/st/power_mgmt/blinky;
- samples/boards/st/power_mgmt/wkup_pins;
I've measured consumption for each low-power mode:
- low-power sleep ~1.72mA;
- stop mode ~324uA;
- standby mode ~2.2 uA;
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Adds additional MPU memory permissions to userspace applications by
default. This change addresses an MPU fault encountered when running
tests/kernel/common and tests/drivers/adc/adc_api.
This approach opens additional memory locations up to user space access.
This assumes that end users of applications will tune the MPU regions for
the needs of that application.
Signed-off-by: John Batch <john.batch@infineon.com>
Interrupt vectors for lpuart1 and lpuart2 are swapped according to the
reference manual RM0503 table 54.
Fixes the usage of the interrupt-driven uart API.
Signed-off-by: Axel Utech <utech@sofiha.de>
This reverts commit 53375e95ba.
Some boards are failing with:
OverflowError: can't convert negative int to unsigned
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Network Coprocessor on SiWx91x owns a large part of the flash. Zephyr
is not expected to access to theses areas.
However, it is still technically possible to access these. In addition, we
prefer the DTS contains a comprehensive and transparent description of the
hardware. So update the DTS with the real partitioning of the SoC.
Reference documentation is available here[1].
[1]: https://www.silabs.com/documents/public/application-notes/
an1416-siwx917-soc-memory-map.pdf
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
mspm0lx series comes with various SoC's which varies in RAM,
Flash size and also with peripherals. Add support for all
the currently available SoC's with basic template.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
PIO interrupts are useful for some of the virtual
peripherals, so describe them in the DT.
This has no direct implications to existing drivers.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Adding initial support for NXP FRDM K32L2B3 board.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
dts: arm: nxp: Fix SRAM node name
Fix address part of the SRAM node name.
Change the SRAM start address definition to lower
case hexadecimal to be consistent.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Moved pinctrl dtsi files for slwrb4250b and slwrb4255a from the soc
directory to the board directory as is done in other boards.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
