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4 Commits

Author SHA1 Message Date
Carlo Caione
afa65e4bbe tests: kernel/cache: Do not invd the whole cache 
That is dangerous and a big no-no. Remove it.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2024-03-01 14:08:34 +01:00
Daniel Leung
48349351a9 tests: kernel/cache: skip i-cache range tests if Xtensa MMU 
With MMU enabled on Xtensa, user_buffer is not marked as
executable. Invalidating the i-cache by region will cause
an instruction fetch prohibited exception. So skip all
i-cache tests, instead of just the range ones to avoid
confusions of only running the test partially.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
 2023-12-18 12:25:04 +01:00
Carlo Caione
826d35b188 tests: cache: Add missing cases 
Some test cases are missing. Add those back.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2023-04-20 14:56:09 -04:00
Carlo Caione
b504d388ea tests: cache: Add cache test 
This is useful to prove that the implementation of the API is done
correctly.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2022-12-01 13:40:56 -05:00