Commit Graph

540 Commits

Author SHA1 Message Date
Flavio Ceolin
b1abe896e6 intel_adsp: ace: Fix function return
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':

zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]

   47 |   return;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-08 21:13:29 -04:00
Kumar Gala
a22ac090db soc: xtensa: intel_adsp: ace_v1x: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
37fc9552e6 soc: xtensa: intel_adsp: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Tom Burdick
572ccd531d intel_adsp: Use device tree to enable/disable each HDA driver
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.

Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.

By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-08 14:33:06 -04:00
Marc Herbert
08baba2520 soc/intel_adsp: cavstool: add support for DSP power state: D3
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.

More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
  not alive.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Marc Herbert
ef4cd76970 soc/intel_adsp: cavstool: new parameter wait_fw_entered(timeout_s)
Add a new timeout_s parameter that can also be 'None' = infinite.

No functional change. Required to add future support for DSP power
state: D3

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Flavio Ceolin
158a87018c intel: adsp: Simplify PM
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().

This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-07 02:10:11 -04:00
Enjia Mai
faff3f7ecc soc: xtensa: partial fix of socket misuse and refine the code
1. Improve the firmware transfer reliability by fixing the misuse
of the socket. Fix the most frequent occurence of the common `recv()`
bug described here:

https://docs.python.org/3/howto/sockets.html#using-a-socket

The longer term fix is to switch to a higher level API like Python
Remote Objects.

2. Not rely on the client's command to disconnect. Previously we
rely on the SIGINT to send stop_command to the server, but it does
not work well in some environments. Refine the whole logic and the
sever disconnect service by checking if the client is alive or not.

These changes make the client-server-based cavstool more stable.

Fixes #46864

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-06 20:38:41 -04:00
Andrey Borisovich
e0b1d81acb soc: intel_adsp: added casting for C++ compiler in soc.h
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
aa253d9ab1 soc: intel_adsp: reading HP SRAM banks count for ACE1X from Devicetree
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
92725e3102 soc: adsp: sram: Assorted cosmetic fixes
General code style fixes.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
7291c518a0 soc: ace: Organizing include headers
Properly prefixing some include files with "zephyr", also organizing
the order they are included.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
65fbfcd480 soc: ace: Move power management to its own file
Move power management hooks to its own C file.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
e4a3e2d8b6 intel_adsp: Unify cavs and ace timers
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
e0e2dbf6f0 soc: ace1x: provided register names to addresses
Provided register names to hardcoded addresses in ace_v1x-regs
header.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
8792dd800d soc: ace1.x: use common code
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
0b15a8d3ef soc: ace_v1x: pm_state_exit_post_ops implementation
Implementation of the function used during the exit from the lower power
states.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
8940b9cae5 soc: ace_v1x: pm_state_set implementation
This patch implements pm_state_set function for ACE platforms.

This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
cc9f82de44 soc: ace_v1x: soc_adsp_halt_cpu implementation
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
b49d794966 ace: multiprocessing: add polling for core powered up confirmation
Poll for CPA bit by which HW confirms that the core has been powered up.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
090b01e73c ace: multiprocessing: enable secondary core boot through ROM
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
b330a05539 intel_adsp: add a new series to support Meteorlake
Meteorlake support as part of the Intel ADSP family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
782b083686 soc: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 11:00:45 -04:00
Enjia Mai
a1e388ea2e soc: xtensa: keep the CAVS old flasher still works
Keep the cavstwist.sh it is still working by specifying an
environment variable when CAVS_OLD_FLASHER is set. Provide
a fallback once the client-server-based tool does not work
well in some conditions.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-02 06:06:19 -04:00
Daniel Leung
1277c38797 cavs: disable timer interrupt on cpu power off
Since the timer interrupt is delivered to all cores at the same
time, it needs to be disabled (or masked) to prevent it from
waking a suspended CPU core.

Note that there is no need to re-enable (unmask) timer
interrupt separately as it is being taken care of in
smp_timer_init() when the CPU re-inits itself.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-07-01 14:04:50 -04:00
Guennadi Liakhovetski
3748bdcad6 xtensa: return to idle() when booting sporadically
To power down secondary cores on cAVS 2.5 platforms the primary core
enables the power-saving mode for the respective secondary core and
waits until that core enters idle() and executes the waiti
instruction at which point the core should enter a lower-power mode.
However, that core can then also automatically wake up and execute
its reset path if, e.g. an interrupt is delivered to it. However, it
isn't entirely clear which events are able to wake up cores from that
state. Disabling interrupts on the interrupt controller didn't seem
to prevent that from happening completely. In particular a specific
ADL notebook seems to be susceptible to this problem. Checking for
such sporadic boots and returning to idle fixes the problem.

BugLink: https://github.com/zephyrproject-rtos/zephyr/issues/46372
BugLink: https://github.com/thesofproject/sof/issues/5733
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-07-01 14:04:50 -04:00
Glauber Maroto Ferreira
fb919a75ba soc: esp32/s2/c3: pinctrl: update pin init macros
Updates pin initialization macros to make use
of pin grouping.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-01 16:22:18 +00:00
Ederson de Souza
afed5e4010 soc/xtensa/intel_adsp/tools: Dial back stream reset sleep
A full second is too much, and since "Ack local interrupt before
processing IPC" patch, it doesn't seem necessary. This whole second
wait would break tests that log too much content, as the firmware
is already running during the reset - and the host script wouldn't read
the contents, thus some of the logs would be overwritten.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-30 06:13:30 -04:00
Jaroslaw Stelter
8632986746 soc: intel_adsp: Add lib_code module type.
External libraries can contain processing module code or common library
code. Library manager need to distinguish between both type of modules
for proper loading.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-06-29 10:41:59 -04:00
Ederson de Souza
7ab8607e71 soc/xtensa/intel_adsp/tools: Ack local interrupt before processing IPC
It seems a race can happen between the host acknowledging a DONE
interrupt and the DSP being able to mark some IPC as done. To avoid
this, the host script now always acknowledges the DONE interrupt
_before_ processing the IPC message.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-28 14:56:57 -04:00
Ederson de Souza
4fd8d474ec soc/xtensa/intel_adsp/tools: Do not use grep Perl extensions
They may be disabled in some environments (such as Gentoo based
developer mode on Chromebooks). Use extended regular expressions
instead.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-27 15:41:00 -05:00
Ederson de Souza
0ce9446978 soc/xtensa/intel_adsp: Add cAVS clock driver
Simple driver that allows one to choose the clock speed of xtensa cores.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-27 12:42:04 +02:00
Lauren Murphy
318e6db239 debug: coredump: add xtensa intel adsp, support toolchains
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.

Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.

Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-06-23 15:44:45 -04:00
Sylvio Alves
54ca96f523 soc: esp32: opt to make device handles in dram
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.

For now this is a workaround until this can be handled in loader script.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:43 +02:00
Sylvio Alves
8e04acab3b linker: esp32: fix flash linking reference
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:32 +02:00
Anas Nashif
bc38f25178 intel_adsp: fix typo PLATFORM_INIT_LPRSRAM -> PLATFORM_INIT_LPSRAM
Fix typo in define preventing initialization of LPSRAM.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-22 12:16:41 +02:00
Rafal Redzimski
bd46470167 xtensa: intel_adsp: add rom jump address definition
Add the definition of address which is used by ROM to jump to FW.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-21 14:01:01 -04:00
Anas Nashif
09cd218cde intel_adsp: use arch_proc_id() instead of local function
Use arch_proc_id interface instead of locally defined function.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-21 10:48:28 +02:00
Stephanos Ioannidis
c40949a389 soc: esp32s2: Drop IRAM_ATTR from forward declarations
This commit drops the `IRAM_ATTR` macro from the function declarations
because:

1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.

2. Section attributes need not be specified for forward declarations.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-06-20 10:28:06 +02:00
Krzysztof Chruscinski
c5f2cdef09 logging: Remove logging v1 from the logging
Remove v1 implementation from log_core and all references in the tree.
Remove modules used by v1: log_list and log_msg.
Remove Kconfig v1 specific options.
Remove Kconfig flags used for distinction between v1 and v2.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-06-16 10:51:15 -04:00
Anas Nashif
fa843d308e i2s: remove s1000 i2s driver
Remove intel_s1000_crb drivers. The board is no longer available or
supported in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-13 16:19:51 -04:00
Anas Nashif
798a552daf boards: intel_s1000_crb: remove board/soc
Remove the intel_s1000_crb board. it is no longer available or supported
in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-13 16:19:51 -04:00
Jaska Uimonen
44ef4c4737 dma/cavs_hda: write aligned size to DGMBS register
Write aligned size also to DGMBS register. At least SOF with linux
host and cavs25 seems to need this for the dma to trigger.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-06-09 11:34:32 +02:00
Andy Ross
12eda76939 arch/xtensa: Add CCOUNT-based timing API
Expose the Xtenesa CCOUNT timing register (the lowest level CPU cycle
counter) using the arch_timing_*() API.

This is the simplest possible way to get this working.  Future work
might focus on moving the rate configuration into devicetree in a
standard way, integrating with the platform clock driver on intel_adsp
such that the reported cycle rate tracks runtime changes (though IIRC
this is not a SOF requirement), and adding better test coverage to the
timing layer, which right now isn't exercised anywhere but in
benchmarks.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-06-07 19:04:42 +02:00
Ederson de Souza
3209bc1a4a soc/xtensa/intel_adsp/tools: Make cavstool.py DSP resetting more stable
When using more than one core on cavs25, some hangs were made
"persistent", as it seems not all cores were being properly reset, thus
compromising tests - if a test hangs for any reason, subsequent tests
that were not restrict to a single CPU would also fail.

This patch mitigates these issues by two changes:
  - Closely mimics SOF Linux driver way of loading the firmware. So,
    explicit stall and reset (and "unstall" and "unreset") of cores, with
    appropriate checks that states have been reached;
  - More generous sleep before resetting the stream.

Also, the status of ADSPCS (Audio DSP Control and Status) register is
logged more thoroughly to aid debugging in case new issues arise.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-07 11:51:37 +02:00
Enjia Mai
415b47c4ac soc: xtensa: rename the cavstool back for backward compatibility
The name change for cavstool.py has also broken the backward
compatibility for SOF testing. Rename cavstool_server.py back
to cavstool.py. Keep the functionality still as same as the previous
one.

And also update the documentation of it.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-06-06 22:46:52 +02:00
Enjia Mai
027dcdeae8 soc: xtensa: fix the direct usage of log only and loading firmware
The new client-server-based cavstool has broken the SOF CI testing
due to not considering that loading firmware and output log directly
without daemon is still necessary. Fix that when it is not running
as a daemon.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-06-06 22:46:52 +02:00
Enjia Mai
a0c64cbbb1 boards: xtensa: Activate the intel_adsp west runner
Make the intel_adsp west runner starting to work on all the
intel_adsp boards. Changes include:

1. Make the cavstool.py work as a service in remote host
   ADSP board and rename it to cavstool_server.py.

2. Active the runner and adds a common board.cmake file to
   specify the default signing key for cavs boards.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-06-05 14:13:57 +02:00
Enjia Mai
01b0c73ece soc: intel_adsp: add a client-server based cavstool tool
The cavstool_client.py is a client use to communicate with
the firmware loading and running server which dealing with
the requests from the intel_adsp west runner. It supports:

1. Download firmware to remote ADSP host and running.
2. Send the ADSP log messages back to client.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-06-05 14:13:57 +02:00
Fabio Baltieri
e24314f10f include: add more missing zephyr/ prefixes
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-05-27 15:20:27 -07:00