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soc: intel_adsp: reading HP SRAM banks count for ACE1X from Devicetree

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Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This commit is contained in:
Andrey Borisovich 2022-07-05 01:29:41 +02:00 committed by Anas Nashif
parent 283953b090
commit aa253d9ab1
2 changed files with 5 additions and 2 deletions
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1
samples/subsys/audio/sof/boards/intel_adsp_ace15_mtpm.conf
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@ -2,7 +2,6 @@ CONFIG_INTEL_DMIC=y
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=22
CONFIG_RIMAGE_SIGNING_SCHEMA="mtl"
CONFIG_IPC_MAJOR_4=y
CONFIG_COMP_SRC=n

6
soc/xtensa/intel_adsp/common/sram.c
View File

@ -16,7 +16,11 @@
#define DELAY_COUNT 256
#define LPSRAM_MASK(x) 0x00000003
#if defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
#define SRAM_BANK_SIZE (128 * 1024)
#else
#define SRAM_BANK_SIZE (64 * 1024)
#endif
#define EBB_SEGMENT_SIZE 32
#if !defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
#define PLATFORM_INIT_HPSRAM
@ -26,7 +30,7 @@
#define PLATFORM_HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE)
BUILD_ASSERT((DT_REG_SIZE(DT_NODELABEL(sram0)) % SRAM_BANK_SIZE) == 0,
"sram0 must be divisible by 64*1024 bank size.")
"sram0 must be divisible by 64*1024 bank size.");
/*
* Function powers up a number of memory banks provided as an argument