It was being included twice. Now it's included once. CI requires a commit
description.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Without this, setting a value of 0 leaves the bits unchanged rather than
zeroing them.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Add the driver for the clock control of the new stm32h5.
See the corresponding Ref Man to get the clock scheme :
HSI, CSI, HSI48, HSE, LSE, and 2 or 3 PLLs
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The U5-series was missed when adding if-defs around enable / disable
of the backup domain access, this patch makes sure the U5-series
is handled correctly.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
We get a compiler warning in this code with arm clang due to using
the wrong enum type for the variable. The enum should be of
type `enum periph_clk32k_src` so replace VBR_CLK32K_SRC_PIN_XTAL
with PERIPH_CLK32K_SRC_PIN_XTAL.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add clock control support for UART controllers found in i.MX SoC family.
This change moves clock gating out of respective `soc.c` files and into
clock controller's `clock_control_on`/`_off` methods, allowing for
dynamic clock state control, and setup via Device Tree bindings.
This is especially important on SoCs, where Zephyr is sharing the bus
with cores running other OSes, such as might be the case for i.MX 8MM.
Unfortunately, Zephyr doesn't possess an ability to represent clock
hierarchy (e.g. via DT's `assigned-clocks` property), so clock source
and frequency still need to be hardcoded in aforementioned `soc.c`
files.
Signed-off-by: Artur Rojek <artur@conclusive.pl>
Use `uintptr_t` to cast a pointer to integer type for `clock_name`.
While at it, also remove an unused variable.
Signed-off-by: Artur Rojek <artur@conclusive.pl>
The STM32H730 series has a variant built with SMPS. It uses
`stm32h730xxq.h` header file instead of `stm32h730xx.h`, which has the
SMPS macro defined.
This commit adds the `SOC_STM32H730XXQ` configuration option to allow
the build system include the proper header file. With this change,
boards can enable `CONFIG_POWER_SUPPLY_DIRECT_SMPS` to set up the power
supply for the CPU.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add clock rate definitions for MIPI and LCDIF peripherals, to enable
retrival of these peripheral clock rates at runtime.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.
Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add PLLI2S support within clock_control driver.
This implementation is compatible with "st,stm32f412-plli2s-clock"
binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PLLI2S support within clock_control driver.
This implementation is compatible with "st,stm32f4-plli2s-clock"
binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This enables the MCO clock output pin to be configured through Kconfig on
stm32l4 devices.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This enables the MCO clock output pins to be configured through Kconfig on
stm32f7 devices.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Program the right trim control register for mec150x.
This fixes uart debug console output issue.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
On stm32wb, M0 core may enable and disable CLK48 when using RNG.
Lock related hsem to prevent M0 to disable CLK48 when it doesn't need it
anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In some case, we may need to describe a domain clock for a device
while there is no way to configure it (ex: USB clock set on PLL_Q output
on F405 devices > It is not selectable).
Then, configuring a device clock domain in the clock_control driver
will allow to retrieve its subsys rate.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Current divisor is 10000000 (should be 1000000).
For example, ESP32_CLK_CPU_240M / 10000000 == 24 MHz (incorrect).
Signed-off-by: Chris Wilson <christopher.david.wilson@gmail.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
On STM32F1 series, configure USB(/OTGFS) prescaler based on DT.
When prescaler is set, PLL output clock is not divided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The timer_ids contain timers that belong to any bus.
So, It should recognize with entire id, not only the CLOCK_ID_BIT part.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DT_COMPAT_GET_ANY_STATUS_OKAY is not suited for the node's existing check.
(This macro returns the stem of the DTS macro name,
the stem part is not a defined symbol.)
Instead, it should use the DT_HAS_COMPAT_STATUS_OKAY macro.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32_clock_control_init is needed for implementation of custom
pm_state_exit_post_ops.
Signed-off-by: Artur Lipowski <Artur.Lipowski@hidglobal.com>
Routines called by users to release (and perhaps stop) the HFCLK
cannot synchronize with only the `hfclk_users` atomic variable,
because a thread can be preempted right after it clears the proper
bit in that variable but before the HFCLK is actually requested to
stop, and another user can then request the HFCLK to start. This can
result in HFCLK being stopped right after it was requested to start
and in `hfclk_users` holding an incorrect value.
Fix this by locking interrupts in those routines until the HFCLK is
stopped.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The Flash latency depends on the sysclock
In case of the stm32F7 the regulator overdrive mode is set
depending on the sys clock freq.
The overdrive must be set before the first LL_SetFlashLatency.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the stm32U5, when the sysclock is > 55 MHz, the EPOD booster
must be configured before the PLL1 is enabled (see refMan).
This is the case when sysclock is on PLL1 sourced by MSIS or
HSE higher than 16MHz.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to configure domain clock, clock_control_configure should be
used instead of clock_control_on which is only useful for bus clock gating.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are
clock source is based upon an OTP setting. Add logic to adjust
clock source based on OTP value. If the OTP value is ever changed
this fix will allow calcluation of correct clock rate.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
clock_stm32_ll_common.h was missing <stdint.h> and <zephyr/device.h>. It
turns out things worked because <zephyr/init.h> has a forward
declaration of struct device.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
mcux HAL pollutes namespace with stuff like ARRAY_SIZE, MIN, MAX, etc.
Luckily it only defines them if not already defined, so we can play with
include order to "fix" the problem. Move the infamous soc.h (which
includes HAL) after other Zephyr includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files using time_units.h API did not include it, e.g. for
sys_clock_hw_cycles_per_sec.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
