Adds support for GD32 timer
Note: Currently, it is not supporting RISC-V(GD32V) devices.
It needs some work on the interrupt controller first.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The timer_ids contain timers that belong to any bus.
So, It should recognize with entire id, not only the CLOCK_ID_BIT part.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DT_COMPAT_GET_ANY_STATUS_OKAY is not suited for the node's existing check.
(This macro returns the stem of the DTS macro name,
the stem part is not a defined symbol.)
Instead, it should use the DT_HAS_COMPAT_STATUS_OKAY macro.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Change Summary:
Update Base addr to set direction to use Aligned IP base address instead
of Port Base Address. Port Base Address + offset to direction register
will set incorrect value for Port B,C & D. For ex: In cases when more than
1 port is configured on the same IP, the DTS node for port B will start
at offset 0xC. Calculating the port using Port Base will yield offset of
PORTB DIR register which is at offset 0x10 from Aligned Base, and as a
result will result in setting DIR register of PORTC instead.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
Change Summary:
Moving the setting of Pin direction before setting/clearing the pin
configured as output for the change to correctly take place.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
For architectures that rely on a PCIe controller (for example, ARM64),
scanning the PCI space will only succeed after the controller has
initialized. Therefore, in the presence of PCIe controller, the PCIe
initialization is bumped to the next system init level.
In the past, drivers like ivshmem would do a late scan of the PCI space
in case the early scan failed; however, the cited commit removed this
feature and ivshmem fails for ARM64. This commit fix this by making the
early scan succeed.
Fixes: a96016d747 ("drivers: ivshmem: Remove unnecessary BDF lookup ...")
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Only include the MSI header when ivshmem-doorbell is employed, as the
ivshmem data structures already use the same protection for msi-related
structures.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
The ivshmem code does not use any platform-specific code; therefore,
remove the dependency to the soc interface.
No functional change intended.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add a Kconfig option allowing users to configure the transfer timeout
value, as the default 500 ms may not be sufficient in specific cases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In multi-image environment, after jump to the image we can have UART in
unexpected state. Reset UART to default state to make sure that UART is
initialized properly and won't cause system to crash or hang.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
In multi-image environment, after jump to the image we can have running
timer with interrupts enabled. If interrupt is triggered, the asserts
in the driver can cause a crash.
This patch also adds 'resets' property for all timer nodes.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.
This patch extends existing implementation to support this type of
register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This driver exposes STM32 RCC reset functionality through reset API.
Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This function is responsible for checking if combination of msize,
mburst and FIFO level is allowed. Possible combinations can be found in
ST documentation, eg. Table 36. FIFO threshold configurations, RM0402
9.3.13 FIFO chapter.
Previously there was no 'break' or '__fallthrough' in msize switch which
caused compilation errors. Since we are confirming that combination is
correct, 'break' statements should be used.
Besides of introducing missing 'break' statements, this patch moves
'return false' from switch to the end of the function. This makes code
shorter and easier to understand, because we have only correct
combinations.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
The poll_in function of the NuMicro UART driver was using the UART_Read
function from the Nuvoton HAL, which is blocking. Replace it with a
non-blocking implementation.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Add the resume API function for the dma driver of the stm32U5 serie.
That completes the suspend API function.
Controlling the SUSPF bit of the GPDMA CR register is enough
to suspend/resume the channel.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There is no need to reset the channel else DMA config is lost and
channel should be enabled again in case of resume.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The USB_DC_STM32 help message started to miss some
STM32 MCU families. Overtime, the message will
get bigger if we continue to list family names.
Removed family names to simplify the message and
avoid periodic modifications.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.
Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
STM32 counter driver uses switch statement in which cases don't end
with break or return intentionally.
Affected switches in counter driver check status of all timer channels
(maximum 4 channels), but the number of channels is not determined
during compilation. In switch, we jump to channel with highest number
and then check other channels with lower numbers.
Compiler can warn about it, so this patch adds information that it was
intentional.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
The HSI48 is enabled by clock control driver.
It is no more done by each driver that requires this clock
However when using rng or sdmmc or bluetooth/ipm or usb,
the HSI48 clock must be present in the DTS.
Add a warning for this particular check but keep the deprecated
HSI48 clock enable : keeping for legacy but to remove later.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds support for get_config and get_direction functions
for the nct38xx IO expander family.
Also applies the clang-format changes.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This commit fixes the comment and adds the missing assignment of
return value from i2c read byte command in the nct38xx driver.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add support for setting the help description for each entry in a dictionary
command. Currently the syntax string alone may not provide sufficient
description of its entry. This commit also helps keep the help messages
consistent with existing style.
Signed-off-by: Xinyang Tan <xinyang.tan@delve.com>
Now, multiple tx buffers can be used to send packets,
so that the packet size can exceed tx buffer size.
Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
STM32H7X and STM32F4X ETH HAL Drivers now provide a new api.
This commit only adds a new Kconfig option
Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
The transmit mutex is not needed while checking the packet size,
so we acquire the lock after checking the size and
return early if it is too big.
Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
