According to the Zephyr Coding Guideline all switch statements
shall be well-formed. Add a default case with break and comment
to avoid static analysis tool to raise a violation that there is no
default case.
Also, I think, in all cases above no need to use "break",
because they already are using "return".
Found as a coding guideline violation (MISRA R16.1) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
An 'if' (expression) construct shall be followed by a compound
statement.
Add braces to improve readability and maintainability.
Found as a coding guideline violation (MISRA R15.6) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
Function types shall be in prototype form with named parameters
Found as a coding guideline violation (MISRA R8.2) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
Variable "level" in function z_vrfy_log_filter_set() has type unsigned.
But it is been checked if "level >=LOG_LEVEL_NONE" and
LOG_LEVEL_NONE is 0. It means check if unsigned is ">= 0" in Z_OOPS().
That is logically wrong, because unsigned is ">=0" by default.
Remove that check, to avoid static analysis tool raise
violation
Found as a coding guideline violation (MISRA R14.3) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
If radio driver supports transmission security we need an option
to disable transmission security which by default is done by OT stack
for Thread v1.2
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
Simplify the the MCP320x instance initialization macro a bit by
converting it to use the new DT helper macros for SPI.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Simplify the LMP90xxx instance initialization macro a bit by converting
it to use the new DT helper macros for SPI and GPIO.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
commit d31ed3be04 enabled multiple
instances but when multiple instances are actually used the code does
not compile
Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
Most of the code for the three exception functions is identical so use
macros to make things easier to read.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Use the context switch macro for z_arm_cortex_r_svc to be more clear
about the svc call being executed.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Zephyr SDK is not supported on OS X, however, Zephyr toolchain can be
built on OS X using Crosstool-NG.
Currently, trusted-firmware-m CMakeLists.txt only supports `zephyr` and
`gnuarmemb` toolchains which prohibits building TF-M on OS X using
Zephyr toolchain built with Crosstool-NG.
docs:
https://docs.zephyrproject.org/latest/getting_started/toolchain_3rd_party_x_compilers.html#crosstool-ng
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
On the STM32F429I-DISC1 PA2 is used for MEMS_INT2, which is driven low
by U3 by default. Connecting it to USART2 TX causes the MCU to try and
drive it high at the same time, causing excessive power consumption.
Dropping the usart2 node since the USART2 alternate pins are also used
for other things, and no other UARTs of the device has a pair of TX/RX
pins available on this reference board in its default configuration.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Arrange device-tree files of npcx7 series by following steps:
1. Move device-tree declarations of npcx family to npcx.dtsi.
2. Leave specific device declarations of npcx7 series to npcx7.dtsi.
3. Move chip series related mapping tables such as
npcx7-miwus-wui-map.dtsi and so on to npcx/npcx7 folder.
4. Move common device-tree declarations used in each npcx series to
npcx-miwus-wui-map.dtsi and so on to npcx folder.
Then, the npcx device-tree folders are arranged to:
dts/arm/nuvoton
|--npcx
| |--npcx7
| | |--npcx7-miwus-wui-map.dtsi
| | |--npcx7-alts-map.dtsi
| | |--.....
| |--npcx-miwus-wui-map.dtsi
| |--npcx-alts-map.dtsi
| |--.....
|
|--npcx.dtsi
|--npcx7.dtsi
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update release notes for 2.6, and the vulnerabilities page to mention
CVE-2021-3581. This CVE is under embargo until Sept 4, 2021.
Signed-off-by: David Brown <david.brown@linaro.org>
Mention the example application as a major enhancement and provide a
link to its repository.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update to the Zephyr build configuration CMake package documentation
with description on how a Zephyr build configuration CMake package can
be located outside a Zephyr workspace.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fixes: #35890
The current implementation of Zephyr build configuration CMake package
only allows the build configuration package to be placed inside a
Zephyr workspace.
This commit extends the usability by allowing users to locate the
Zephyr build configuration CMake package outside the Zephyr workspace
and then refer to the package using
`-DZephyrBuildConfiguration_ROOT=<path>`
`set(ZephyrBuildConfiguration_ROOT <path>)`
This allows users greater flexibility in their workspace layouts.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
* Added a bullet about new storage subsystem feature
* Moved disk subsystem changes into disk section
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The tabulator handler creates a single structure if it is handling
dynamic commands. If the currently processed dynamic command has a
dynamic subcommand they both share the same structure.
As a result tabulation operation may result in undefined behaviour.
As a solution, a new structure was introduced to keep subcommand
information.
Fixes#35926.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Fix incorrect and redundant use of ticker user id ULL_LOW
instead of ULL_HIGH when setting up a connection using a
mayfly to disable LLL context. Also, the LLL context pointer
is invalid, where node rx is passed instead of LLL context.
Use the ULL disabled callback when done event has not yet
been processed, or a direct connection setup in ULL_HIGH
context when ULL is already disabled (reference count is
zero) is sufficient.
Regression introduced in commit 30f260dfaa ("Bluetooth:
controller: Fix adv/scan context access post release").
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
The caller saved registers were restored both as caller saved and
callee saved registers, i.e. register 0-15 were restored into
both register 0-15 and 15-31.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Shell log backend depends on logging being enabled. Lack of this
dependency leads to compilation failure when logging is disabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
For some reason a few drivers were not converted to the new device PM
callback signature. The reason may be because the device PM part is
compiled only when CONFIG_PM_DEVICE=y, a condition not enabled in CI by
default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The data-sjw value was incorrectly written to the NBTP register when it
should be written to the DBTP register.
This fixes a regression introduced by
5e0ca9b41e.
Signed-off-by: Christoph Steiger <c.steiger@lemonage.de>
Updates the frdm_k64f board documentation to clarify that the J-Link
OpenSDA firmware version depends on the DAPLink bootloader version.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This board got forgotten when we migrated the older APIC_TIMER users.
Now the platform is SMP by default and the older driver refuses to
build.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
ACRN build and configuration is non-trivially complicated, and so far
integration documentation has been mostly missing, and users have had
to get by via copying from existing integration efforts with minor
changes, leading to repeated mistakes and persistent confusion. This
is an attempt to document the process from first principles, with an
eye toward informing integrators (not me!) who might come by later to
better automate things. Some of the content is going to look remedial
to someone already familiar with e.g. ACRN configuration or EFI boot.
This simply replaces the pre-existing docs, which were for earlier
versions of ACRN where Zephyr was launched from the service OS instead
of the now-standard pre-launch VM mode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
SMP is working now, make a 2-cpu configuration default for this
device.
Note that this requires changes to the default ACRN build
configuration! In hybrid.xml, you need to specify multiple physical
CPUs for the VM to uses, e.g.:
<vm id="0">
...
<cpu_affinity>
<pcpu_id>0</pcpu_id>
<pcpu_id>1</pcpu_id>
</cpu_affinity>
</vm>
Failing to build with this change will result in the system hanging at
boot trying to start up a CPU that won't run.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The ACRN hypervisor uses 0, 2, 4, 6 as its local APIC IDs for
virtualized CPUs and not the 0, 1, 2, 3 defaults we have.
(I hate this feature, having to manually (!) probe and code these
things in C isn't scaling. Zephyr needs to do the probing on its own
somehow, even if it's an offline tool in Linux or something.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The 16 bit bootstrap code for SMP CPUs was using the 286-era "lmsw"
instruction (load machine status word) to set the protected bit in CR0
(which is the modern evolution of the same register), presumably
because this is 16 bit code and we can't move a dword into CR0.
But that's wrong, because the full instruction set *is* available in
real mode on a 386, you just have to use a operand size prefix to get
to it, which the assembler emits for you automatically when you use
the .code16 directive.
Write this conventionally and use modern (e.g. 1986-era) instructions.
It also has the advantage of not confusing much more modern
hypervisors like ACRN by issuing instructions they (and I!) never knew
existed.
Fixes#35076
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Because of a historical misunderstanding, by default the ACRN
hypervisor wants to load Zephyr at address 0x1000 and enter the binary
at that same address. This entry point corresponds to the __start
symbol of the build they were given, which is a 1-cpu non-SMP
configuration. Unfortunately, when we build with
CONFIG_MP_NUM_CPUS=1, the code in locore.S #if's out the 16 bit entry
point for the auxiliary CPUs at the start of the section. So in the
build ACRN received, the start address happened to be 0x7000, the same
address we need to launch the AP processors from.
That's right: under ACRN, the SAME ADDRESS used to enter the OS in 32
bit mode needs to be used later to boot CPUs running in 16 bit real
mode!
The solution, such as it is, is to put a 32 bit jump at the entry
address which hops to the 32 bit OS entry code, and then scribble NOP
instructions over that jump once we get there so that the next time we
reach that address (in real mode) we fall through to the correct
entry.
This patch should be considered a temporary workaround. While it
works on all x86 hardware, it's not really needed. A much better
solution would be to eliminate the locore linker region entirely
(which causes other headaches) and enter the Zephyr binary in a 32 bit
address somewhere in the contiguous high memory area. All that locore
is needed for is the 16 bit bootstrap code for SMP processors, which
is ~6 instructions and can be copied in from the kernel at runtime.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
