Add second instance to be tested on nrf54h20dk. uart120 is a fast UARTE
which works on fixed pin locations. It is not available for cpuppr core.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
One of the test case is performing long transfers using 1k buffers.
For some targets there may be not enough RAM to perform such
transfers. Make long buffer length configurable.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for running tests with DCache enabled & put DMA buffers
in a nocache memory region to avoid coherency issues.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
For some reason the host gcc (11 & 12) does not believe
rx_buf_size is constant. Let's work around it by using the
sizeof() expression it is initialized to instead.
This fixes a build error when targetting native targets
which use the host gcc:
tests/drivers/uart/uart_async_api/src/test_uart_async.c:236:34:
error: expression in static assertion is not constant
236 | BUILD_ASSERT(rx_buf_size <=
sizeof(tdata.rx_first_buffer), "Invalid buf size");
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Commit eb44414af9 modified
test_single_read for early rx buf release.
The commit assumed that tdata.last_rx_buf points to either &tdata.rx_buf[0]
if the driver releases the first buffer or at &rx_buf[5] if the first
buffer is not released. However, where tdata.last_rx_buf points to depends
on the timeout given to uart_rx_enable(), making the test flaky.
This commit modifies the test by keeping track how many bytes have been
received in the first and second buffers.
The function tdata_check_recv_buffer() validates that the sent data
matches the received bytes which may have been split between first and
second buffer.
This fixes the uart_async_api test on the xmc45_relax_kit.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Modify the test to not rely on assumption that RX buffer is released
when it is fully released. RX buffer maybe released after any RX_RDY
event within the buffer, e.g. after each timeout driver may be
switching to the new buffer.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adds overlay and config for xmc45_relax_kit.
The Kconfig entry CONFIG_SPEED_OPTIMIZATIONS=y must be set
to pass the test at baudrate 921600 bps.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This commit configures the testcase to run on the
stm32u5x5 target boards. USART2 is selected
Pins Tx and Rx (PD5 PD6 on CN9) must be connected on the HW board
to pass the test.
The USART transfer uses the GP DMA transfer with request
27 and 26 on 2 DMA channels (0-15).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures the testcase to run on the
stm32u585 target boards. USART3 is selected
Pins Tx and Rx (PD8 PD9 on CN14) must be connected on the HW board
to pass the test.
The USART transfer uses the GP DMA transfer with request
28 and 29 on 2 DMA channels (0-15).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure through an overlay file, the nucleo_wb55rg board
for running the tests/drivers/uart/uart_async_api.
DMAMUX is used for transfer on channels 0 & 1 with
LPUART peripheral request 17 & 16.
No hw flowcontrol for this test.
Connect pin A0 & A1 of CN8 to PASS the test.
Note that I2C3 pin assignment might conflict (PC0 & PC1).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Initialize devices at compile time. Also fix some ready check problems
(e.g. in async test readiness failure just resulted in a printk, but
test continued...).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move to use DEVICE_DT_GET instead of device_get_binding as we
work on phasing out use of DTS 'label' property.
Also, fixed issue that change exposes with SEGGER RTT testing
in that in some platforms the device getting selected for the
RTT test was not the RTT device.
Signed-off-by: Kumar Gala <galak@kernel.org>
This PR adds support for the RT1060_EVKB as a variant of the RT1060 EVK.
Blinky app tested locally on RT1060_EVKB.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f746 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f746zg board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f767 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f767zi board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
add nxp,loopback mode to boards with LPUART. This will enable testing
the UART async api without a physical loopback connection.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
define uart peripheral that can be connected as a loopback using
external jumper for all boards this test can be run against.
Additionally, all RT boards require DMA memory to be noncacheable. Move
SRAM to DTCM for all RT10xx series boards, and to noncacheable OCRAM for
RT11xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Intention of the test is to abort rx few bytes after start of
transmission (before it is completed). Previously, thread was busy
waiting after start of TX and aborted RX from that context. However,
it may happen that CPU is busy handling UART transfer and
k_busy_wait prolongs beyond full transfer which results in test
failure.
Move rx_abort to k_timer timeout which is run in interrupt
context.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a test case that ensures that uart_rx_enable() can be successfully
called after RX is disabled with uart_rx_disable() and also when it is
disabled automatically after the provided RX buffer is filled up.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Updated uart_rx_enable() and uart_tx() to use timeout given
in microseconds. Previously argument was given in milliseconds.
However, there are cases when milliseconds granularity is not
enough and can significantly reduce a throughput, e.g. 1ms is
100 bytes at 1Mb.
Updated 4 drivers which implement asynchronous API. Updated
places where API was used.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
It enables the usart6 to run the testcase with a DMA
tests/drivers/uart/uart_async_api. DMA2 (of type V1)
is configured on channel 5 (request) streams 7 & 2.
USART Tx and Rx PG14 - PG9 pins (14 & 16 of CN10)
are connected to PASS the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This sets the dts of DMA for using pn the uart 2 i.
The stm32h723 has a DMAMUX and request are 44 and 43 for usart2
The Tx&Rx pins PD5 and PD6 of the usart2 are connected
on the nucleo_h723zg board to pass the test
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add configuration for testing the usart3 through the dma1
on the nucleo_l152re target.This test requires the Tx pin
to be connected to the RX pin on the board.
Pin definition is added for this usart instance.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures usart3 to use dma in uart_async_api test
on nucleo_l552ze_q platform.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit configures usart3 to use dma in uart_async_api test
on stm32l562e_dk platform. Short pin2(PC10) & pin 3 (PC11) of usart3
in CN4 connector on stm32l562e_dk platform.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Adds nucleo_g071rb board to the uart_async_api test.
Therefore additionally add usart1 in board definitions.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This sets the dts of dma for using the uart asynch api.
The stm32l475 has a dmamux with request 2 for Tx/Rx usart4
The Tx&Rx pins (PA0, PA1) of the usart4 are connected
on the disco_l475_iot1 board to pass the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
