This sets the dts of dma for using the uart 6 asynch api. The stm32f767 has a dma V1 with request 5 for Tx/Rx usart6 The Tx&Rx pins (PG14, PG9) of the usart6 are connected on the nucleo_f767zi board to pass the test The CONFIG_DCACHE=n must also be set to disable Dcache. Signed-off-by: Francois Ramu <francois.ramu@st.com> |
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| .. | ||
| main.c | ||
| test_uart_async.c | ||
| test_uart.h | ||