This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add npcm miscellaneous device control and power and clock control
instances.
Add device tree bindings for npcm power and clock control.
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Introduce bindings for Series 2 oscillators: HFRCODPLL, HFRCOEM23,
LFRCO and LFXO.
Add clock tree representation in devicetree `clocks` node.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.
Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
- Create a new compatible: nordic,nrf53x-oscillators, as other series,
e.g. nRF54LX contain a similar but different IP (with PLL control,
etc.)
- Adjust DT: use recommended node name, remove redundant status okay.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This defines raspberrypi,pico-xosc along with a configurable startup
delay multiplier. On some boards, the XOSC takes longer to stabilize.
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
`-` is preferred over `_` in devicetree property names.
Since, change `clk_src`, `clk_div`, and `clk_out_div` to
`clk-src`, `clk-div`, and `clk-out-div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Devicetree binding for NXP mcxc oscillator is not available.
Add the binding to be able to configure the oscillator in devicetree.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add bindings for nrf-fll16m and nrf-lfclk and update in-tree nodes
and boards to use them in place of the fixed-clock binding.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The HFXO and LFXO oscillators have properties which need to be
specified in the devicetree. These properties are used by clock
controllers, which get these properties from the devicetree.
The BICR also contains these properties. For now, the properties
are duplicated in the bicr node in the devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the clock rcc controller,
and the exti interrupt controller based on the stm32h7 rcc bindings.
Three PLL clocks are available.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix a compilation error occurring when a prescaler was set for ADC on F1
and F3 family.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.
A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.
Signed-off-by: Andy Ross <andyross@google.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/clock directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
Some STM32F4xx chips have an R division factor in PLL. Add possibility
to configure that.
Even though the output from the R division is not used, it can be
increased to reduce power consumption.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
