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dts: renesas_ra: Change to describe the division ratio in a numeric

Browse Source 
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.

Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2024-09-12 23:15:27 +09:00 committed by Anas Nashif
parent 7c615f95d2
commit d72a69488c
30 changed files with 175 additions and 175 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/renesas/ek_ra4e2/ek_ra4e2.dts
View File

@ -54,7 +54,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <10 0>;
status = "okay";
};

2
boards/renesas/ek_ra4m2/ek_ra4m2.dts
View File

@ -54,7 +54,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "okay";
};

2
boards/renesas/ek_ra4m3/ek_ra4m3.dts
View File

@ -54,7 +54,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "okay";
};

2
boards/renesas/ek_ra6e2/ek_ra6e2.dts
View File

@ -95,7 +95,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <10 0>;
status = "okay";
};

2
boards/renesas/ek_ra6m1/ek_ra6m1.dts
View File

@ -61,7 +61,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <20 0>;
status = "okay";
};

2
boards/renesas/ek_ra6m2/ek_ra6m2.dts
View File

@ -61,7 +61,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <20 0>;
status = "okay";
};

2
boards/renesas/ek_ra6m3/ek_ra6m3.dts
View File

@ -73,7 +73,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "okay";
};

4
boards/renesas/ek_ra6m4/ek_ra6m4.dts
View File

@ -69,13 +69,13 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "okay";
};
&pclka {
clocks = <&pll>;
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
status = "okay";
};

2
boards/renesas/ek_ra6m5/ek_ra6m5.dts
View File

@ -69,7 +69,7 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "okay";
};

10
boards/renesas/ek_ra8d1/ek_ra8d1.dts
View File

@ -57,20 +57,20 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};
&sciclk {
clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
div = <4>;
status = "okay";
};

10
boards/renesas/ek_ra8m1/ek_ra8m1.dts
View File

@ -80,20 +80,20 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};
&sciclk {
clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
div = <4>;
status = "okay";
};

2
boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
View File

@ -58,7 +58,7 @@
&pll {
clocks = <&hoco>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "okay";
};

2
boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
View File

@ -77,7 +77,7 @@
&pll {
clocks = <&hoco>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <10 0>;
status = "okay";
};

10
boards/renesas/mck_ra8t1/mck_ra8t1.dts
View File

@ -61,20 +61,20 @@
&pll {
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <80 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};
&sciclk {
clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
div = <4>;
status = "okay";
};

8
dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
View File

@ -69,28 +69,28 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};

14
dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
View File

@ -84,7 +84,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <10 0>;
status = "disabled";
};
@ -101,42 +101,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

16
dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
View File

@ -133,7 +133,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "disabled";
};
@ -143,7 +143,7 @@
#clock-cells = <0>;
/* PLL */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -160,42 +160,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

16
dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
View File

@ -143,7 +143,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "disabled";
};
@ -151,7 +151,7 @@
pll2: pll2 {
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -168,42 +168,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

16
dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
View File

@ -78,7 +78,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <12 0>;
status = "disabled";
};
@ -95,42 +95,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
@ -143,7 +143,7 @@
uclk: uclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_USB_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};

16
dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
View File

@ -133,7 +133,7 @@
/* PLL */
clocks = <&hoco>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -143,7 +143,7 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -160,42 +160,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

14
dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
View File

@ -74,7 +74,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <10 0>;
status = "disabled";
};
@ -91,42 +91,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

18
dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
View File

@ -68,7 +68,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <20 0>;
status = "disabled";
};
@ -85,42 +85,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -133,14 +133,14 @@
uclk: uclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_USB_CLOCK_DIV_5>;
div = <5>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

18
dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
View File

@ -99,7 +99,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
div = <1>;
mul = <20 0>;
status = "disabled";
};
@ -116,42 +116,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -164,14 +164,14 @@
uclk: uclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_USB_CLOCK_DIV_5>;
div = <5>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

18
dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
View File

@ -139,7 +139,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -156,42 +156,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -204,14 +204,14 @@
uclk: uclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_USB_CLOCK_DIV_5>;
div = <5>;
#clock-cells = <2>;
status = "okay";
};
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

18
dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
View File

@ -169,7 +169,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "disabled";
};
@ -179,7 +179,7 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -196,42 +196,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -244,7 +244,7 @@
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

18
dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
View File

@ -229,7 +229,7 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
div = <3>;
mul = <25 0>;
status = "disabled";
};
@ -239,7 +239,7 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <20 0>;
status = "disabled";
};
@ -256,42 +256,42 @@
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -304,7 +304,7 @@
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

34
dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
View File

@ -50,13 +50,13 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "disabled";
};
@ -66,13 +66,13 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(0)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(0)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(0)>;
status = "disabled";
};
@ -89,56 +89,56 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -151,7 +151,7 @@
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};

36
dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
View File

@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <1>;
xtal: clock-xtal {
xtal: clock-main-osc {
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
@ -50,13 +50,13 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "disabled";
};
@ -66,13 +66,13 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(0)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(0)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(0)>;
status = "disabled";
};
@ -89,56 +89,56 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -151,7 +151,7 @@
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};

34
dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
View File

@ -50,13 +50,13 @@
/* PLL */
clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <80 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "disabled";
};
@ -66,13 +66,13 @@
#clock-cells = <0>;
/* PLL2 */
div = <RA_PLL_DIV_2>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(0)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(0)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(0)>;
status = "disabled";
};
@ -89,56 +89,56 @@
cpuclk: cpuclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
bclkout: bclkout {
compatible = "renesas,ra-cgc-busclk";
clk-out-div = <2>;
@ -151,7 +151,7 @@
fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_8>;
div = <8>;
#clock-cells = <2>;
status = "okay";
};

2
dts/bindings/clock/renesas,ra-cgc-pclk.yaml
View File

@ -8,7 +8,7 @@ compatible: "renesas,ra-cgc-pclk"
include: [clock-controller.yaml, base.yaml]
properties:
clk-div:
div:
type: int
required: true
description: Prescale divider to calculate the subclock frequency from the