diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 2bf7a9d3ff0..aa1e8f9435d 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 9cb8d8b77bb..9ccde6acd8a 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index 09701ac9923..21867f1dbe4 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -54,7 +54,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 29571eb28a2..6e068eb55bd 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -95,7 +95,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index 631f2d1384c..53fc329b048 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -61,7 +61,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 19721a46a20..d498d6448e5 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -61,7 +61,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index db9031340a9..141292d9f7e 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -73,7 +73,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index b156f6f1e52..866232d5c7f 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -69,13 +69,13 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; &pclka { clocks = <&pll>; - clk-div = ; + div = <2>; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index 902e281984e..3cb4ebe3ba5 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -69,7 +69,7 @@ &pll { clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index e17bf02718c..4449e566c2d 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -57,20 +57,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index df94f202a15..0e3b6ec3cd5 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -80,20 +80,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index b0aa5b48f08..2efab7438b5 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -58,7 +58,7 @@ &pll { clocks = <&hoco>; - div = ; + div = <2>; mul = <20 0>; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index 847f5528813..fbde0caf013 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -77,7 +77,7 @@ &pll { clocks = <&hoco>; - div = ; + div = <1>; mul = <10 0>; status = "okay"; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index ea060222879..6cd4cf53eb8 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -61,20 +61,20 @@ &pll { clocks = <&xtal>; - div = ; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "okay"; }; &sciclk { clocks = <&pll>; - clk-div = ; + div = <4>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index bb230163816..8c60af4b83d 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -69,28 +69,28 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 6feb69d4a43..3f403525ada 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -84,7 +84,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -101,42 +101,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 7ed9fdabd78..6abfa96b0c8 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -133,7 +133,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -143,7 +143,7 @@ #clock-cells = <0>; /* PLL */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -160,42 +160,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 1277844b1b8..fbfe3b5e36c 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -143,7 +143,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -151,7 +151,7 @@ pll2: pll2 { compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -168,42 +168,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 93ea6751e9c..4603b53044d 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -78,7 +78,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <12 0>; status = "disabled"; }; @@ -95,42 +95,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; @@ -143,7 +143,7 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index b070022ee5f..d8d31ceb55a 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -133,7 +133,7 @@ /* PLL */ clocks = <&hoco>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -143,7 +143,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -160,42 +160,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 7576bb0dcd3..d1d9bfad58d 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -74,7 +74,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <10 0>; status = "disabled"; }; @@ -91,42 +91,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index af177168321..2415350363b 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -68,7 +68,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -85,42 +85,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -133,14 +133,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index a06241a95b3..db5488f79f2 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -99,7 +99,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <1>; mul = <20 0>; status = "disabled"; }; @@ -116,42 +116,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -164,14 +164,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index 197be43a3fc..0e233cd7d6f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -139,7 +139,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -156,42 +156,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -204,14 +204,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <5>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 0310f61e65d..da800071362 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -169,7 +169,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -179,7 +179,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -196,42 +196,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -244,7 +244,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 91d95e288d8..e266560fb5f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -229,7 +229,7 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <3>; mul = <25 0>; status = "disabled"; }; @@ -239,7 +239,7 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <20 0>; status = "disabled"; }; @@ -256,42 +256,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -304,7 +304,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 5b00642bae3..3db4898ccb2 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index c184c1432e2..cb22fd3357a 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <1>; - xtal: clock-xtal { + xtal: clock-main-osc { compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 3f4fb717f35..de851f6bf47 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -50,13 +50,13 @@ /* PLL */ clocks = <&xtal>; - div = ; + div = <2>; mul = <80 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -66,13 +66,13 @@ #clock-cells = <0>; /* PLL2 */ - div = ; + div = <2>; mul = <96 0>; - divp = ; + divp = <2>; freqp = ; - divq = ; + divq = <2>; freqq = ; - divr = ; + divr = <2>; freqr = ; status = "disabled"; }; @@ -89,56 +89,56 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <2>; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <4>; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; clk-out-div = <2>; @@ -151,7 +151,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk-div = ; + div = <8>; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml index 1aac515882d..798b1d3569f 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -8,7 +8,7 @@ compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] properties: - clk-div: + div: type: int required: true description: Prescale divider to calculate the subclock frequency from the