The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
nRF5340 PDK board was deprecated in v2.5.0 release
and is removed now from the tree.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With this change it is possible to share all configurations
related to CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION without
including the clock calibration configurations.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Clock calibration should only be used when RC source is used.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
AHB3 bus support is added for compatible series.
Additionaly, fix condition for AHB2 support and fix
formatting
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
core-macros.h includes other files not part of the xtensa HAL, make this
esp32 specific
Fixes#31301
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
-The STM32F410RB has no AHB2 bus so LL_AHB2_GRP1_EnableClock() and
LL_AHB2_GRP1_DisableClock() should not be called for this soc.
-The interrupt table had to be changed because of no OTG_FS_WKUP_IRQn
(no USB OTG at all).
Signed-off-by: Hans Unzner <hansunzner@gmail.com>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Provide a utility function to compute PLL VCO input range so that it
can be re-used for other PLLs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Line break on #error directive is confusing github and ending up
breaking syntax highligthing in github UI which makes me nervous
during review.
Convert error message to a one liner.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch enables the rtc clock on the stm32g4 soc
from STMicroelectronics.
Even if the set by default (reset value of theRCC_APB1ENR)
the bit is marked as 1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
After system reset, the PWR interface clock must be enabled
by setting the PWREN bit of the RCC_APBENR1
This sequence is needed to use the RTC.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Convert driver(s) to DEVICE_DEFINE instead of DEVICE_AND_API_INIT
so we can deprecate DEVICE_AND_API_INIT in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some Clocks have ifdefs only for clock_control_on but are missing
them for clock_control_off.
Additionally return ahb_clock clock frequency for stm32g0
STM32_CLOCK_BUS_IOP in stm32_clock_control_get_subsys_rate.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Use the clock devicetree node as the source of object name and other
information used when defining the device structure.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
An event was not handled by the clock control resulting in assert
and lack of notification about clock readiness.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a Kconfig option (enabled by default) the enables the low-frequency
oscillator (LFXO) functionality on the XL1 and XL2 pins in the nRF53
SoC initialization routine. This cannot be done in the clock control
driver, as it was done so far, because that won't work in a setup where
the application core image does not use the system clock at all.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Stable API change: modify parameters of clock_control_async_on which
previously took a structure which contains list node, callback and user
context. Removing list node and replacing structure with two parameters:
callback and user context. List node is removed because it has no use
in current API.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.
Signed-off-by: Eric Hay <EHay@sierrawireless.com>
Add const modifier for hal instances, clock devices pointer, and module
base address in npcx drivers to prevent driver functions change them
unexpectedly.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
1. clock: move the call for MSI hardware auto calibration enabling
before the control of MSI enable to ensure its execution in all
cases.
2. counter: add call for MSI hardware auto calibration enabling after
the LSE enabling and after possible backup domain reset that may
clear MSIPLLEN.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
Algorithm for waiting for clock stabilization was failing in case when
it was waiting for clock availablity and clock was already available
before function was called. That is because nrfx_clock_is_running
was returning false because XTAL was already started but not yet
running.
Added a check for current LF source, if XTAL is picked that indicates
that RC is already running because of two stage startup procedure.
Added documentation of lfclk_spinwait with explanation of two stage
approach.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Pins used for external LF clock source must be configured as
used by peripheral to allow using LFXO on network side.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Enabled going to idle when waiting for low frequency clock.
Added 2 stages of starting LF clock when XTAL is used. First
stage is starting RC and then when it is ready XTAL is started.
It is done to get event/interrupt when RC is ready which means
that LF clock is available (but not stable).
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added configuration for approach to starting system clock source.
There are 3 options: no wait, wait untill available, wait until
stable.
Added support for those modes in clock control driver which handles
low frequency source clock.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
VCO input frequency can be checked and set during compile time.
It unfortunately does not work for output frequency because macros in
HAL are defined together with uint32_t type.
This also fixes wrong check in case of HSI used as PLL source.
Signed-off-by: Jan Pohanka <xhpohanka@gmail.com>
Fixed 'line length exceeds 80 columns' warning by shortening the clock
controller device name from NPCX_CLOCK_CONTROL_NAME to
NPCX_CLK_CTRL_NAME.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This is a follow-up to commit 701e9befe4.
The NRFX_POWER Kconfig option should be enabled together with USB_NRFX,
not with CLOCK_CONTROL_NRF, as the USB driver is the actual user of
the nrfx POWER driver.
This patch adds also missing initialization of the nrfx POWER driver
and refactors a bit the usb_init() function introduced in the commit
mentioned above, so that it does not redefine the DT_DRV_COMPAT macro
and uses for conditional compilation the same Kconfig option that is
the dependency of NRFX_USBREG.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.
This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Renamed nrf clock control driver file since it does no long control
POWER peripheral.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
