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drivers: clock_control: stm32g0: Enable the Q divisor on g0X1 variants

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The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.

Signed-off-by: Eric Hay <EHay@sierrawireless.com>
This commit is contained in:
Eric Hay 2020-10-07 11:16:01 -07:00 committed by Carles Cufí
parent 31fca27d83
commit e51b24b429
3 changed files with 9 additions and 16 deletions
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9
drivers/clock_control/Kconfig.stm32g0
View File

@ -30,6 +30,15 @@ config CLOCK_STM32_PLL_P_DIVISOR
help
PLL P VCO divisor, allowed values: 2-32.
config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_STM32G031XX || SOC_STM32G071XX)
default 2
range 2 8
help
PLL Q VCO divisor, allowed values: 2-8.
Limited to STM32G0X1 variants.
config CLOCK_STM32_PLL_R_DIVISOR
int "PLL R Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL

8
soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx
View File

@ -13,12 +13,4 @@ config NUM_IRQS
int
default 30
config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 2 8
help
PLL Q VCO divisor, allowed values: 2-8.
endif # SOC_STM32G031XX

8
soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx
View File

@ -12,12 +12,4 @@ config SOC
config NUM_IRQS
default 32
config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 2 8
help
PLL Q VCO divisor, allowed values: 2-8
endif # SOC_STM32G071XX