The main stack size is too small by default in many boards.
Increase the size to 1024 bytes which works fine with
sam_e70_xplained board.
Fixes#31342
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This patch replace CONFIG_GPIO_SIFIVE_N_PRIORITY into interrupt-cell
of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch replace CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY into
interrupt-cell of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The BBC micro:bit v2 is a mini-computer that has been
designed to make the coding fun and easy to learn.
The micro:bit v2 is completely programmable so you can
easily bring your ideas to life! From making games to
creating music and even controlling robots.
The micro:bit comes with neat hardware such as a 25 LED
display, buttons, in-built speakers, Bluetooth 5 & Mesh
connectivity and sensors for temperature, motion & light.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_GPIOS_TO_PSEL(): converts a devicetree GPIO phandle
<&gpioX pin flags> to the "PSEL style" registers found in
nRF SoC family IPs. The conversion is done at
build time and relies on devicetree properties.
- NRF_DT_CHECK_GPIO_CTLR_IS_SOC(): make sure a GPIO controller
in a phandle-array property is one of the SoC GPIO controllers
by checking its compatible is nordic,nrf-gpio.
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This property is required information for extracting PSEL bits relevant
to peripheral pinmux from this node.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add some details to help new users learn how to manage the nodes
for compatibles corresponding to IP blocks on Nordic SoCs.
The focus is on IP blocks where the pinmux is configured in
devicetree. These typically have individual properties for each pin,
like a SCK pin on a SPI peripheral, which correspond directly to a
PSEL register value. These violate the usual devicetree convention of
using a 'foo-gpios <&gpioX ...>' phandle property and work in ways
that only make sense if you understand the underlying register map, so
it's worth explaining them a bit more carefully.
Skip these two bindings, which have no drivers: nordic,nrf-i2s.yaml,
nordic,nrf-pdm.yaml.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We recently added a generated devicetree bindings index. Link to it
from the bindings page in the Guides section of the documentation so
it's easier for beginners to find.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Before we had a bindings index in the documentation, the generated
header file was (somewhat unfortunately) often our best reference for
what a particular binding or property within a binding ends up doing,
so it made good sense to put the description in the generated file.
Now that we have HTML documentation that's a bit more digestible than
the generated file, though, we can just point users at that. Do that
and remove the inline description from the generated file.
This makes it possible to put C-style multiline comments in the
descriptions themselves, which will be done in subsequent patches.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This macro returns a node's full path, given its node identifier.
The entire path to a node is useful information for the user which can
be added to build-time error messages.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Remove the boards and shields lists from the 'usage' target output.
That might have been readable at some point long ago in Zephyr's
history, when only a few boards were available, but right now it's
obscuring the high level targets we really want 'usage' to print.
Instead, add 'boards' and 'shields' targets which the user can run to
get those lists, and reference them from the 'usage' output. This
makes 'usage' squintable again. We use the new list_boards.py script
from the 'boards' target.
Reference the 'help' target from 'usage' as well, and drop the
recommendation that people run '--target help' from the 'west build
--help' output for the 'west build --target' option. The canonical
place to look is 'usage' now.
Use the new list_boards.py code from 'west boards' as well, which
allows us to add the board's directory as a format string key, in
addition to its name and architecture.
Keep west-completion.bash up to date. While doing that, I noticed that
a bunch of references to this file refer to a stale location, so fix
those too.
Finally, the 'usage' output is what we print for a failed board or
shield lookup, so that needs to be updated also. Handle that by
invoking boards.cmake and a new shields.cmake in CMake script mode to
print the relevant output.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This script is essentially a Python rewrite of the CMake code we're
using to print boards in cmake/boards.cmake, plus some extra features.
Having this in Python will simplify some later adjustments to our
'usage' build system target in ways that will make its output easier
to read, while simultaneously making 'west boards' more useful.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In #31192 stm32 uart driver uart_irq_rx/tx_ready functions were
modified to take into account status of irq.
While it seems wlecome for TX (based on uart client's implementation),
this is not correct for RX.
Revert change in uart_stm32_irq_rx_ready function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In std_print(), the log arguments were casted to uint32_t before
being sent further to the output function.
For integer types which can not be represented by uint32_t, the
degraded user experience may be acceptable.
However, for string arguments, the output function will eventually
dereference the pointer, so if the "char *" can not be represented
by uint32_t, bad things are going to happen. In practice you will see
this on 64-bit systems where sizeof (char *) is 8 byte and addresses
higher than 0x80000000.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Increased stacks required for RISC-V 64-bit CI to pass. Most of these
were catched by the kernel stack sentinel.
The CMSIS stacks are for programs in samples/portability.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The testcase allocates lots of stack space, many KiB, for RISC-V
64-bit in the mbedtls bignum functions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit improves portability somewhat on machines where sizeof
(int) is less than sizeof (void *). Note that the implementation is
still not portable and will fail when you start using addresses which
can not be represented by "int cast to unsigned int".
On RISC-V 64-bit with RAM on 0x80000000 we previously got hit by
E: Exception cause Load access fault (5)
ld s0,16(a0)
a0: 0xffffffff80025610
(The int should probably be changed to intptr_t if possible.)
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The app_kernel test hangs or crashes on qemu_x86_64 when more than
one CPU is enabled. So limits the number of CPUs to 1 even when SMP
is enabled.
This issue has probably been masked for some time because the test
was previously marked as being "slow".
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The test now uses CONFIG_HAS_NEWLIB_LIBC_NANO rather than
toolchain_allow to determine if newlib nano is available.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Upgrade board specification to use the VirtIO board.
Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The CONFIG_FLOAT_HARD config previously enabled the C (compressed)
ISA extensions (CONFIG_COMPRESSED_ISA). This commit removes that
dependency.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
We compile objects with -mcmodel=medany. Now also give -mcmodel=medany
to the GCC front-end when linking to pick up the corresponding
multilibs.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
1. Exclude the CODE UNREACHABLE line while generating coverage report.
2. Exclude the memory domain deprecated API when calculating code
coverage.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
1. Add a null dynamic name testing for device_get_binding().
2. Add a driver which initialization failed in SYS_INIT.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
The main stack size is too small by default in many boards.
Increase the size to 1024 bytes which works fine with
sam_e70_xplained board.
Fixes#31343
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
1. Remove the error test cases that trigger assertion.
2. Refine the NULL and invalid kobject parameter test case.
3. Use the common fatal error handler to reduce code.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
First, the maximum heap size must fit in 31 bits worth of chunks
because the internal 32-bit field holding the size is shared with
the `used` bit.
Then the mention of a 256-byte block in the doc is no longer
relevant. That pertained to the previous allocator implementation.
And ditto for the HEAP_MEM_POOL_MIN_SIZE kconfig option.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Replace marco function, defined(), with IS_ENABLED() in host sub-devices
driver implementation. In this PR, we won't replace the macros which
cause -Wimplicit-function-declaration warning if related configuration
is not enabled or its type is not boolean..
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Allow vendor specific increase of user operation capacity for LLL, to
support queuing additional ticker operations from lower link layer
context. These would typically take place in lll_xxx_prepare.
Signed-off-by: Morten Priess <mtpr@oticon.com>
For Bluetooth Mesh, counter shall be increasing by one when
every try to establishing friendship.
Counter to be used when create friendship security material.
So this value shall be consist between friend and lpn.
Due to zephyr bluetooth mesh send previous counter, after that
it will automatically increase one, which will result in the
incorrect generation of friend key when key rephase.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Add test for the P4 Work Queue gadget. Includes coverage sections
detailing all elements of the API, and a reasonably extensive stress
suite that will saturate the device for 1k events.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This adds a somewhat special purpose IPC mechanism. It's intended for
applications which have a "work queue" like architecture of discrete
callback items, but which need the ability to schedule those items
independently in separate threads across multiple CPUs. So P4 Work
items:
1. Can run at any Zephyr scheduler priority and with any deadline
(this feature assumes EDF scheduling is enabled)
2. Can be submitted at any time and from any context, including being
resubmitted from within their own handler.
3. Will preempt any lower priority work as soon as they are runnable,
according to the standard rules of Zephyr priority scheduling.
4. Run from a pool of worker threads that can be allocated efficiently
(i.e. you need as many as the number of CPUs plus the number of
preempted in-progress items, but no more).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Needing to check the current cycle time (which involves a spinlock and
register read on most architectures) is wasteful in the scheduler
priority predicate, which is a hot path. If we "burn" one bit of
precision (and document the rule), we can do the comparison without
knowing the current time.
2^31 cycles is still far longer than a live deadline thread in any
legitimate realtime app should ever live before being scheduled.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The default of coredump is to dump all RAM as defined in
the linker script. However, this takes a while on boards
with bigger memory space, and would slow down automated
testing due to the need to grab all the data via serial.
So change it to dump minimal memory, as this would still
test the memory dumping capability.
Fixes#28547
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
