Before this fix the board init function were called too early, before
the gpio driver was initialized. Because of the the board controller
for the serial port was not enabled properly.
This commit fixes this issue.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Hex firmware file is flashed by default if JLink is used. Since all
of the SiLabs dev boards have an on-board JLink, enable generating hex
file.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Add test to check if uart_irq_is_pending() correctly returns 0 (meaning
there are no more RX and TX pending interrupts) when all RX and TX data
is processed.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Currently CMSDK uart_irq_is_pending does not use RX and TX interrupt
bits found in INTSTATUS register to check for pending interrutps but
rather it checks for pending interrupts indirectly by checking if RX and
TX buffers are, respectively, full and empty, i.e. it checks bits 0 and
1 in STATE register instead of bits meant for interrupt status found in
INTSTATUS register.
That is particularly problematic because although a RX interrupt implies
a RX buffer full and a TX interrupt implies a TX buffer empty, the
converse is not true. For instance, a TX buffer might be empty for all
data was processed (sent to serial line) already and no further data was
pushed into TX buffer so it remained empty, without generating any
additional TX interrupt. In that case the current uart_irq_is_pending
implementation reports that there are pending interrupts because of the
following logic:
/* Return true if rx buffer full or tx buffer empty */
return (UART_STRUCT(dev)->state & (UART_RX_BF | UART_TX_BF))
!= UART_TX_BF;
which will return 1 (true) if STATE[0] = 0 (TX buffer is empty), since
UART_TX_BF = 1, so STATE[0] != UART_TX_BF, which is true (assuming here
for the sake of simplicity that UART_RX_BF = 0, i.e. RX buffer is empty
too).
One of the common uses of uart_irq_is_pending is in ISR in contructs
like the following:
while (uart_irq_update(dev) && uart_irq_is_pending(dev)) {
if (uart_irq_rx_ready(dev) == 0) { // RX buffer is empty
continue;
}
// RX buffer is full, process RX data
}
So the ISR can be called due to a RX interrupt. Upon finishing
processing the RX data uart_irq_is_pending is called to check for any
pending IRQs and if it happens that TX buffer is empty (like in the case
that TX interrupt is totally disabled) execution gets stuck in the while
loop because TX buffer will never transition to full again, i.e. it will
never have a chance to have STATE[0] = 1, so STATE[0] != UART_TX_BF is
always true.
This commit fixes that undesirable and problematic behavior by making
uart_irq_is_pending use the proper bits in the interrupt status register
(INTSTATUS) to determine if there is indeed any pending interrupts.
That, on the other hand, requires that the pending interrupt flags are
not clearly automatically when calling the ISR, otherwise
uart_irq_is_pending() will return immediatly false on the first call
without any data being really processed inside the ISR. Thus, because
both RX and TX buffer (FIFO) are only 1 byte long, that commit clears
the proper interrupts flags precisely when data is processed (fifo_read
and fifo_fill) or when the interrupts are disabled (irq_rx_disable and
irq_tx_disable).
Finally, that commits also takes the chance to update some comments,
specially regarding the need to "prime" when enabling the TX interrupts
(in uart_cmsdk_apb_irq_tx_enable()). The need to "prime" can be verified
in the CMSDK UART reference implementation in Verilog mentioned in the
"Arm Cortex-M System Design Kit" [0], on p. 4-8, section 4.3,
in cmsdk_apb_uart.v. In that implementation it's also possible to verify
that the FIFO is only 1 byte long, justifying the semantics that if
buffers are not full (STATE[0] or STATE[1] = 0) they are _completly_
empty, holding no data at all.
[0] https://documentation-service.arm.com/static/5e8f1c777100066a414f770b
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
* Removed leading 0 from slot0_partition starting offset
* Fixed slot1_partition starting offset
This fixes the following warnings:
nucleo_g0b1re.dts.pre.tmp:1749.36-1752.5: Warning
(unit_address_format):
/soc/flash-controller@40022000/flash@8000000/partitions/
partition@0C000:unit name should not have leading 0s
warning: unit address and first address in 'reg' (0x3e000) don't match
for /soc/flash-controller@40022000/flash@8000000/partitions/
partition@31000
Signed-off-by: Raúl Sánchez Siles <rsanchezs@k-lagan.com>
The "spi-max-frequency" property already exists, but was unused. This
now sets the SPI clock frequency to this value (limited to 24MHz) once
initialisation is complete.
Due to the nature of the SPI API, it is necessary to have two separate
configuration structures to switch clock speed as some SPI drivers only
compare pointers to detect changes.
Fixes: #32996
Signed-off-by: Rich Barlow <rich@bennellick.com>
Enabling DAC support for STM32 nucleo_f429zi in device tree.
Documentation has been updated.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
With this change, L2CAP/LE/CFC/BV-06-C can be supported when using
BT_RPMSG and the others HCI transports.
Depending on CONFIG_BT_HCI_RESERVE, the HCI transport requires extra
headroom in a BT buffer.
Signed-off-by: Ryan Chu <ryan.chu@nordicsemi.no>
This commit enables test_spi_loopback sample application for
Nucleo_F207zg. test_spi_loopback was executed under the following case
sceanarios on SPI-1:
a. With DMA
b. No DMA - No Interrrupts
c. No DMA - Interrupts Enabled
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling SPI support for Nucleo-F207zg in device tree.
This has been tested with test_spi_loopback on SPI-1.
Documentation has been updated.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling SPI support for STM32F2 platforms in dtsi.
This has been tested with test_spi_loopback on SPI-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Now that we can use the adafruit_2_8_tft_touch_v2 shield with
mimxrt685_evk_cm33 and frdm_k64f boards, start building the display
driver and lvgl samples for these boards in CI.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Configures the pinmux for the Arduino D9 pin to allow using it as a
gpio. This is needed by the adafruit_2_8_tft_touch_v2 shield for
cmd-data-gpios.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds Arduino header pin mappings to the mimxrt685_evk board to enable
using it with the adafruit_2_8_tft_touch_v2 shield and lvgl sample.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
In acda9bf9ce new macros were introduced to support a virtual memory
map. Adjust these macros also for AArch64. This also fixes a problem
when building Zephyr when CONFIG_KERNEL_VM_BASE is not the same as
CONFIG_SRAM_BASE_ADDRESS
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
hwinfo_get_define_id returns and ssize_t with the size og the copied
id in case of success or negative value otherwise.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
hwinfo_get_define_id returns and ssize_t. Positive value with the
size of the copied id in success or a negative value in case
of error.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This CL introduces the implementation of configurating PSL input pads
and setting PSL_OUT to inactive level for ultra-low power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update the backport action to 1.1.1-1, which adds support for issue
creation when a backport fails.
In our case, label the issue with the "backport" and "bug" labels.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
PWR clock is required for various operations.
It is enabled by default in clock control driver,
but disabled at clock init.
It appears soc init is run after clock control driver init
and hence PWR is disabled to to this piece of code at
soc init level.
Don't disable PWR here.
(But keep PWR clock enable in case of ...).
A whole clock clean up will be required later on,
but waiting for that to happen, this is the safest we can do.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename lib.
Disable AUDIT_LOG in regression sample because of a bug upstream.
Update stm32l562e_dk_ns overlay.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Before this change, the sw reset did not work after power-on, because
I2C commands are only accepted after 20msec (t_START after power-on).
Now the 20msec delay is moved before performing the reset to ensure that
the SW reset command can be executed. An additional 2msec delay is added
after the reset (see datasheet t_START after reset).
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Commit 0a7b65e tweaked the CREATE_OBJ_LEVEL macro in such a way
that it would break the expected sorting order.
For example if you had 2, 19, 20, 30 as the level, we'd end up sort
these to be 19, 2, 20, 30.
Fix this by adding aditional "_" symbol after the init level counter.
That allows to keep correct sort order (for both GNU and MWDT
toolchains) and distinguish init level counter from section suffix
(for MWDT toolchain).
Fixes zephyrproject-rtos#33464
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The fatal log now contains
- Trap type in human readable representation
- Integer registers visible to the program when trap was taken
- Special register values such as PC and PSR
- Backtrace with PC and SP
If CONFIG_EXTRA_EXCEPTION_INFO is enabled, then all the above is
logged. If not, only the special registers are logged.
The format is inspired by the GRMON debug monitor and TSIM simulator.
A quick guide on how to use the values is in fatal.c.
It now looks like this:
E: tt = 0x02, illegal_instruction
E:
E: INS LOCALS OUTS GLOBALS
E: 0: 00000000 f3900fc0 40007c50 00000000
E: 1: 00000000 40004bf0 40008d30 40008c00
E: 2: 00000000 40004bf4 40008000 00000003
E: 3: 40009158 00000000 40009000 00000002
E: 4: 40008fa8 40003c00 40008fa8 00000008
E: 5: 40009000 f3400fc0 00000000 00000080
E: 6: 4000a1f8 40000050 4000a190 00000000
E: 7: 40002308 00000000 40001fb8 000000c1
E:
E: psr: f30000c7 wim: 00000008 tbr: 40000020 y: 00000000
E: pc: 4000a1f4 npc: 4000a1f8
E:
E: pc sp
E: #0 4000a1f4 4000a190
E: #1 40002308 4000a1f8
E: #2 40003b24 4000a258
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Introduce a new software trap 15 which is generated by the
ARCH_EXCEPT() function macro.
The handler for this software trap calls z_sparc_fatal_error() and
finally z_fatal_error() with "reason" and ESF as arguments.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Unexpected software traps ("ta" instruction) are now handled by the
fatal exception handler and eventually end up in z_fatal_error().
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Changed chan type to int in the test_timeout function which follows
change in the api to always use int for channel parameter.
Added assert to check that channel was successfully allocated in
test_resetting_cc().
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
There was an inconsistency in the API as z_nrf_rtc_timer_chan_alloc
returned int but other function were using uint32_t for channel
argument. Updated api to use int32_t everywhere.
Update nrf_802154 driver which was using this api to use int32_t.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
