Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add support for the NXP KE1xF SoC to the eDMA driver. The KE1xF supports
m2m DMA transfers from sources 60 to 63.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
DMA driver shall be initialized before any of its
clients. Right now, its initialization priority is
lower than that of UARTs. So, increase its init
priority to support future async uart drivers.
Signed-off-by: Jun Li <jun.r.li@intel.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Replace individual device instance definitions with the macro that
expands to the equivalent change.
F='struct device DEVICE_NAME_GET'
git grep -l "$F" \
| xargs sed -i -r \
-e "s@$F"'\(([^)]*)\);@DEVICE_DECLARE(\1);@'
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.
There are a few exceptions:
- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
would require more time to convert than I have at the moment. For the
sake of expediency, just inline the DT_HAS_DRV_INST expansion for
now in these cases.
- SoC drivers which are explicitly single-instance (like the nRF SAADC
driver). Again for the sake of expediency, drop a BUILD_ASSERT in
those cases to make sure the assumption that all supported SoCs have
at most one available instance is valid, failing fast otherwise.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This reverts commit 90cc723e65.
Using `DMAC_CHCTRLA_TRIGACT_BLOCK` breaks SERCOM UART peripheral DMA
operations (DMA-based asynchronous UART transmit operation only sends
the first byte and does not proceed any further).
The `DMAC_CHCTRLA_TRIGACT_BURST` with `DMAC_CHCTRLA_BURSTLEN(0)` is a
special case utilising the "internal FIFO", according to the datasheet
(see DS60001507E; 22.6.2.8), and should always be specified for
peripheral data transfer operations.
Also it is worth noting that Atmel and other third-party drivers use
the aforementioned "internal FIFO" configuration for peripheral data
transfers as well.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The channel direction for a V1 DMA is not allowed to be memory to memory
and there is a check in place for this. However, the check is being
performed on the stream prior to actually configuring the stream. This
results in the check always failing regardless of the channel direction.
The check has been modified to be performed on the incoming
configuration.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
This patch prepares the dma and introduces the dmamux on soc series
which supports this feature for memory/periph transfers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch is disabling the dma channel before reloading
source and dest for memory and peripheral addresses
Then the channel is enabled to re-launch the transfer.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
define the irq handler in case of DMA V1 or V2,
for the stm32x soc series
with DMA V1 raise Fifo Error if enabled
with V2, handle the Global Interrupt
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Return an error if the direction of the channel is wrong
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move tables declaration as they are only used locally for now
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Control values when configuring the dma channel
According to the soc specification,
the dma V2 channel counts from 1.
the dma V1 stream counts from 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When a DMA stream is successfully disabled, the function should
immediately return with a success status.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
Fix the definition of DMA_SAM0_IRQ_CONNECT
pre-processor directive, so that it calls
DT_INST_IRQ_BY_IDX macro instead of
DT_INST_IRQ_HAS_IDX macro.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Convert older DT_INST_ macro use in atmel sam0 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in STM32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When building the i2s tests on 96b_argonkey we get the following
warnings:
drivers/dma/dma_stm32.c: In function 'dma_stm32_configure':
drivers/dma/dma_stm32.c:181:2: error: 'periph_addr_adj' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
181 | switch (increment) {
| ^~~~~~
drivers/dma/dma_stm32.c:161:2: error: 'memory_addr_adj' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
161 | switch (increment) {
| ^~~~~~
Fix by initialzing periph_addr_adj and memory_addr_adj to 0.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There will be more instance of that driver, and the initialization
function will the same all the time. That was done wrong as it was not
following the device driver rules.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This driver is going to be used by other SoCs and as such should be
easily configurable through DTS.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
irq_enable() can be directly called from relevant irq config function
and thus voids the necessity to store the IRQ number, saving some
memory.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no such thing as CAVS DMA IP block, the DMA IP block found on
CAVS based chips is made with DesignWare one.
This will help to centralize DW based DMA device into one driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
when DMA IP is enabled on stm32 series,
the heap size must be configured to large value
because of dma channels configuration.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patches defines constants from dma registers
depending on the dma configuration of the stm32 soc
Some devices have 6 or 7 or 8 dma channels per dma instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This checks if the DMA controller supports or not
the memory-to-memory transfers. For DMA Version1,
in the stm32f2xx, stm32f4xx, stm32f7xx series,
only DMA instance 2 is able to transfer mem-to-mem.
For other series, with DMA Version2, there is no such a limitation.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The DMA driver of stm32 used to use `stm32_dma_enable_fifo()`,
which is located in dma_stm32_v1.c to set DMDIS bit, enable
interrupt generation and set FIFO threshold. Now since FIFO
threshold is initialized with `stm32_dma_get_fifo_threshold()`
and interrupt generation is also configured in dma_stm32.c, this
function will only have one job, to configure FIFO mode.
We can add FIFO mode operation in dma_stm32.c directly and
remove it from dma_stm32_v1.c.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Use this short header style in all Kconfig files:
# <description>
# <copyright>
# <license>
...
Also change all <description>s from
# Kconfig[.extension] - Foo-related options
to just
# Foo-related options
It's clear enough that it's about Kconfig.
The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)
git ls-files '*Kconfig*' | \
xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Clean up space errors and use a consistent style throughout the Kconfig
files. This makes reading the Kconfig files more distraction-free, helps
with grepping, and encourages the same style getting copied around
everywhere (meaning another pass hopefully won't be needed).
Go for the most common style:
- Indent properties with a single tab, including for choices.
Properties on choices work exactly the same syntactically as
properties on symbols, so not sure how the no-indentation thing
happened.
- Indent help texts with a tab followed by two spaces
- Put a space between 'config' and the symbol name, not a tab. This
also helps when grepping for definitions.
- Do '# A comment' instead of '#A comment'
I tweaked Kconfiglib a bit to find most of the stuff.
Some help texts were reflowed to 79 columns with 'gq' in Vim as well,
though not all, because I was afraid I'd accidentally mess up
formatting.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Added in commit bb36c0af86 ("dma: Add possibility for up to 3 DMA
Controllers") in February 2017, then never used.
Found with a script.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Defining a symbol with 'menuconfig' just tells the menuconfig to display
any dependent symbols that immediately follow it in a separate menu.
'menuconfig' has no effect on symbol values.
Making a symbol that doesn't have any dependent symbols after it a
'menuconfig' should be avoided, because then you end up with an empty
menu, which is shown as e.g.
[*] Enable foo ---
This is how it would be shown if there were children but they all
happened to be invisible as well.
With a regular 'config', it turns into
[*] Enable foo
Change all pointless 'menuconfig's to 'config's.
See the section on 'menuconfig' on the Kconfig - Tips and Best Practices
page as well.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These calls are not accessible in CI test, nor do they get built on
common platforms (in at least one case I found a typo which proved the
code was truly unused). These changes are blind, so live in a
separate commit. But the nature of the port is mechanical, all other
syscalls in the system work fine, and any errors should be easily
corrected.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move dma.h to drivers/dma.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
During conversion in #16815 a few device tree instance macro aliases
where missed (probably due to them existing to support future SoCs
and so not currently compiled), this fixes their usage.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Implement the get_status DMA API for the SAM0 DMA controller.
The busy field is set only when the selected channel is
actively transferring data (i.e. both enabled and selected by the
arbiter). The direction field is left unset, since that
information is not normally retained by the DMA controller.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Some applications using DMA, such as UART RX, could
need to complete the current DMA transaction earlier than
predefined, based on other termination conditions,
like UART's IDLE interrupts.
In that case, the client needs to know how many data are
still left in DMA transfer buffer so that it can figure
out how many data has been transfered. However, the current
DMA API doesn't provide any information for the client
to learn the transfer buffer information.
And some other information, like whether DMA transfer is busy
or not, transfer direction, etc, could interest a client.
So, added a dma API function to retrieve the current DMA
runtime status.
And implemented the API for STM32F4's DMA while keeping
others unimplemented.
Signed-off-by: Jun Li <jun.r.li@intel.com>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The dma_reload() is useful when there's the need to immediately
and quickly restart the DMA for a new transfer when the current
one is completed. If the operation is not done quickly there
might be underrun or overrun errors and the data flow is broken.
The dma_reload() just does the minimum operations required, i.e.
programming the new src/dst addresses and transfer size.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The existing device_set_power_state() API works only in synchronous
mode and this is not desirable for devices(ex: Gyro) which take
longer time (few 100 mSec) to suspend/resume.
To support async mode, a new callback argument is added to the API.
The device drivers can asynchronously suspend/resume and call the
callback function upon completion of the async request.
This commit adds the missing callback parameter to all the drivers
to make it compliant with the new API.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Checking for the memcopy support using dma_stm32_stream will give wrong
result as it won't get initialised at that point of time. Hence, use
the dma_config member directly for checking the memcopy support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Remove DCACHE_WRITEBACK Kconfig variable definition in Intel S1000
DMA driver. Remove the variable from default configuration as well.
Cache configuration is fixed and the cache operation routines
internally take appropriate action based on the cache configuration.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
In order to make use of the configurable bus width and burst size
options in memcpy mode, lets add configurations bits for the same.
This configuration is derived from the TRM of STM32F446xx Page No. 210
"Memory-to-memory mode" section and verified on 96Boards STM32 Sensor
Mezzanine board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Check clock_control_on return value now that it is checking appropriate
bus is used in the request.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Couple of findings which were revealed after changing
LOG_MODULE_REGISTER macro:
- missing semicolons after LOG_MODULE_REGISTER()
- missing LOG_LEVEL defines
- other
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added a mechanism to refresh DMA buffers without the
need to call the "configure" API every time.
The reload is done after every DMA completion.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Macro is used to create contiguous bitmask between the
arguments passed to the macro.
BITS_PER_LONG is computed as the multiplication of predefined
macros `__CHAR_BIT__` and `__SIZEOF_LONG__`.
Both gcc and clang support these predefined macros.
With this change, replace the redundant defintions of
GENMASK with the new generic macro available.
Fixes#10843
Suggested-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com>
Use user data to replace DMA's device pointer in
the callback function so that the user can retrieve
its context by that private data.
Signed-off-by: Jun Li <jun.r.li@intel.com>
Compilation of this driver was broken by commit 07ff2d5
as reported in issue #10453. This commit is fixing it.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This patch checks whether memory to memory is allowed for the device.
Tested it with tests/drivers/dma with one of the 2 settings:
CONFIG_DMA1_NAME=DMA_0 -> test fails with error message on console
and an error at configuration.
CONFIG_DMA2_NAME=DMA_0 -> test succeeds
Fixes: #7547
Signed-off-by: Alexander Polleti <metapsycholo@gmail.com>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.
The only directory excluded directory was ext/* since it contains
only imported code.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove DMA resource ownership configuration.
Such configuration will be done in an SoC level
initialization routine
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Consistently use
config FOO
bool/int/hex/string "Prompt text"
instead of
config FOO
bool/int/hex/string
prompt "Prompt text"
(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).
The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.
Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The DMA API provides dma_slot field as a method to configure at
runtime which peripheral DMA_request the DMA controller should
select.
This method allows to specify different selections for different stm32
DMA streams. So, all the Kconfig definitions, which by the way where
fixing the same selection for all DMA streams, have been deleted.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The Transfer Complete (TC) interrupt as well as the Memory
Increment (MINC) bits were not enabled for Periperal To
Memory (and Memory to Peripheral) case.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
