bartoszek/zephyr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drivers: dma: move to new logger

Browse Source 
Move to new logger and adapt samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2018-09-17 14:47:17 -05:00
parent f7dac85d15
commit 07ff2d580b
7 changed files with 58 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/dma/Kconfig
View File

@ -49,19 +49,9 @@ config DMA_2_IRQ_PRI
help
IRQ Priority for DMA Controller 2.
config SYS_LOG_DMA_LEVEL
int "DMA Driver Log level"
depends on SYS_LOG
default 0
range 0 4
help
Sets log level for DMA drivers.
Levels are:
0 OFF, do not write
1 ERROR, only write SYS_LOG_ERR
2 WARNING, write SYS_LOG_WRN in addition to previous level
3 INFO, write SYS_LOG_INF in addition to previous levels
4 DEBUG, write SYS_LOG_DBG in addition to previous levels
module = DMA
module-str = dma
source "subsys/logging/Kconfig.template.log_config"
config DCACHE_WRITEBACK
bool "Data Cache Writeback"

24
drivers/dma/dma_cavs.c
View File

@ -16,9 +16,9 @@
#include "dma_cavs.h"
#define SYS_LOG_DOMAIN "dev/dma_cavs"
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
#include <logging/sys_log.h>
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTEr(dma_cavs)
#define BYTE (1)
#define WORD (2)
@ -67,7 +67,7 @@ static void dw_dma_isr(void *arg)
status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS);
if (!status_intr) {
SYS_LOG_ERR("status_intr = %d", status_intr);
LOG_ERR("status_intr = %d", status_intr);
}
/* get the source of our IRQ. */
@ -77,7 +77,7 @@ static void dw_dma_isr(void *arg)
/* TODO: handle errors, just clear them atm */
status_err = dw_read(dev_cfg->base, DW_STATUS_ERR);
if (status_err) {
SYS_LOG_ERR("status_err = %d\n", status_err);
LOG_ERR("status_err = %d\n", status_err);
dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err);
}
@ -135,7 +135,7 @@ static int dw_dma_config(struct device *dev, u32_t channel,
if (cfg->source_data_size != BYTE && cfg->source_data_size != WORD &&
cfg->source_data_size != DWORD) {
SYS_LOG_ERR("Invalid 'source_data_size' value");
LOG_ERR("Invalid 'source_data_size' value");
return -EINVAL;
}
@ -148,11 +148,11 @@ static int dw_dma_config(struct device *dev, u32_t channel,
/* data_size = (2 ^ tr_width) */
tr_width = find_msb_set(cfg->source_data_size) - 1;
SYS_LOG_DBG("tr_width=%d", tr_width);
LOG_DBG("tr_width=%d", tr_width);
/* burst_size = (2 ^ msize) */
m_size = find_msb_set(cfg->source_burst_length) - 1;
SYS_LOG_DBG("m_size=%d", m_size);
LOG_DBG("m_size=%d", m_size);
cfg_blocks = cfg->head_block;
@ -160,7 +160,7 @@ static int dw_dma_config(struct device *dev, u32_t channel,
chan_data->lli = (struct dw_lli2 *)k_malloc(sizeof(struct dw_lli2)
* (cfg->block_count));
if (chan_data->lli == NULL) {
SYS_LOG_ERR("not enough memory\n");
LOG_ERR("not enough memory\n");
return -ENOMEM;
}
@ -211,7 +211,7 @@ static int dw_dma_config(struct device *dev, u32_t channel,
break;
default:
SYS_LOG_ERR("channel_direction %d is not supported",
LOG_ERR("channel_direction %d is not supported",
cfg->channel_direction);
return -EINVAL;
}
@ -362,7 +362,7 @@ static void dw_dma_setup(struct device *dev)
goto found;
}
}
SYS_LOG_ERR("DW_DMA_CFG is non-zero\n");
LOG_ERR("DW_DMA_CFG is non-zero\n");
return;
found:
@ -400,7 +400,7 @@ static int dw_dma0_initialize(struct device *dev)
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
LOG_INF("Device %s initialized", DEV_NAME(dev));
return 0;
}

27
drivers/dma/dma_nios2_msgdma.c
View File

@ -15,8 +15,9 @@
#include "altera_msgdma_descriptor_regs.h"
#include "altera_msgdma.h"
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
#include <logging/sys_log.h>
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(dma_nios2)
/* Device configuration parameters */
struct nios2_msgdma_dev_cfg {
@ -58,7 +59,7 @@ static void nios2_msgdma_callback(void *context)
err_code = 0;
}
SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
LOG_DBG("msgdma csr status Reg: 0x%x", status);
dev_cfg->dma_callback((struct device *)context, 0, err_code);
}
@ -73,29 +74,29 @@ static int nios2_msgdma_config(struct device *dev, u32_t channel,
/* Nios-II MSGDMA supports only one channel per DMA core */
if (channel != 0) {
SYS_LOG_ERR("invalid channel number");
LOG_ERR("invalid channel number");
return -EINVAL;
}
#if MSGDMA_0_CSR_PREFETCHER_ENABLE
if (cfg->block_count > 1) {
SYS_LOG_ERR("driver yet add support multiple descriptors");
LOG_ERR("driver yet add support multiple descriptors");
return -EINVAL;
}
#else
if (cfg->block_count != 1) {
SYS_LOG_ERR("invalid block count!!");
LOG_ERR("invalid block count!!");
return -EINVAL;
}
#endif
if (cfg->head_block == NULL) {
SYS_LOG_ERR("head_block ptr NULL!!");
LOG_ERR("head_block ptr NULL!!");
return -EINVAL;
}
if (cfg->head_block->block_size > MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE) {
SYS_LOG_ERR("DMA error: Data size too big: %d",
LOG_ERR("DMA error: Data size too big: %d",
cfg->head_block->block_size);
return -EINVAL;
}
@ -127,7 +128,7 @@ static int nios2_msgdma_config(struct device *dev, u32_t channel,
dma_block->block_size,
control);
} else {
SYS_LOG_ERR("invalid channel direction");
LOG_ERR("invalid channel direction");
status = -EINVAL;
}
@ -154,7 +155,7 @@ static int nios2_msgdma_transfer_start(struct device *dev, u32_t channel)
/* Nios-II mSGDMA supports only one channel per DMA core */
if (channel != 0) {
SYS_LOG_ERR("Invalid channel number");
LOG_ERR("Invalid channel number");
return -EINVAL;
}
@ -164,7 +165,7 @@ static int nios2_msgdma_transfer_start(struct device *dev, u32_t channel)
k_sem_give(&cfg->sem_lock);
if (status < 0) {
SYS_LOG_ERR("DMA transfer error (%d)", status);
LOG_ERR("DMA transfer error (%d)", status);
}
return status;
@ -185,11 +186,11 @@ static int nios2_msgdma_transfer_stop(struct device *dev, u32_t channel)
k_sem_give(&cfg->sem_lock);
if (status & ALTERA_MSGDMA_CSR_STOP_STATE_MASK) {
SYS_LOG_DBG("DMA Dispatcher stopped");
LOG_DBG("DMA Dispatcher stopped");
ret = 0;
}
SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
LOG_DBG("msgdma csr status Reg: 0x%x", status);
return status;
}

18
drivers/dma/dma_sam_xdmac.c
View File

@ -17,9 +17,9 @@
#include <dma.h>
#include "dma_sam_xdmac.h"
#define SYS_LOG_DOMAIN "dev/dma_sam_xdmac"
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
#include <logging/sys_log.h>
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(dma_sam_xdmac)
#define XDMAC_INT_ERR (XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE)
#define DMA_CHANNELS_NO XDMACCHID_NUMBER
@ -191,20 +191,20 @@ static int sam_xdmac_config(struct device *dev, u32_t channel,
if (cfg->source_data_size != 1 && cfg->source_data_size != 2 &&
cfg->source_data_size != 4) {
SYS_LOG_ERR("Invalid 'source_data_size' value");
LOG_ERR("Invalid 'source_data_size' value");
return -EINVAL;
}
if (cfg->block_count != 1) {
SYS_LOG_ERR("Only single block transfer is currently supported."
LOG_ERR("Only single block transfer is currently supported."
" Please submit a patch.");
return -EINVAL;
}
burst_size = find_msb_set(cfg->source_burst_length) - 1;
SYS_LOG_DBG("burst_size=%d", burst_size);
LOG_DBG("burst_size=%d", burst_size);
data_size = find_msb_set(cfg->source_data_size) - 1;
SYS_LOG_DBG("data_size=%d", data_size);
LOG_DBG("data_size=%d", data_size);
switch (cfg->channel_direction) {
case MEMORY_TO_MEMORY:
@ -231,7 +231,7 @@ static int sam_xdmac_config(struct device *dev, u32_t channel,
| XDMAC_CC_DAM_INCREMENTED_AM;
break;
default:
SYS_LOG_ERR("'channel_direction' value %d is not supported",
LOG_ERR("'channel_direction' value %d is not supported",
cfg->channel_direction);
return -EINVAL;
}
@ -330,7 +330,7 @@ static int sam_xdmac_initialize(struct device *dev)
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
LOG_INF("Device %s initialized", DEV_NAME(dev));
return 0;
}

30
drivers/dma/dma_stm32f4x.c
View File

@ -5,17 +5,19 @@
*
*/
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
#include <board.h>
#include <device.h>
#include <dma.h>
#include <errno.h>
#include <init.h>
#include <logging/sys_log.h>
#include <stdio.h>
#include <string.h>
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(dma_stm32f4x)
#include <clock_control/stm32_clock_control.h>
#define DMA_STM32_MAX_STREAMS 8 /* Number of streams per controller */
@ -166,7 +168,7 @@ struct dma_stm32_config {
#define DMA_STM32_SFCR_MASK (DMA_STM32_SFCR_FEIE \
| DMA_STM32_SFCR_DMDIS)
#define SYS_LOG_U32 __attribute((__unused__)) u32_t
#define LOG_U32 __attribute((__unused__)) u32_t
static void dma_stm32_1_config(struct dma_stm32_device *ddata);
static void dma_stm32_2_config(struct dma_stm32_device *ddata);
@ -184,18 +186,18 @@ static void dma_stm32_write(struct dma_stm32_device *ddata,
static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, u32_t id)
{
SYS_LOG_INF("Using stream: %d\n", id);
SYS_LOG_INF("SCR: 0x%x \t(config)\n",
LOG_INF("Using stream: %d\n", id);
LOG_INF("SCR: 0x%x \t(config)\n",
dma_stm32_read(ddata, DMA_STM32_SCR(id)));
SYS_LOG_INF("SNDTR: 0x%x \t(length)\n",
LOG_INF("SNDTR: 0x%x \t(length)\n",
dma_stm32_read(ddata, DMA_STM32_SNDTR(id)));
SYS_LOG_INF("SPAR: 0x%x \t(source)\n",
LOG_INF("SPAR: 0x%x \t(source)\n",
dma_stm32_read(ddata, DMA_STM32_SPAR(id)));
SYS_LOG_INF("SM0AR: 0x%x \t(destination)\n",
LOG_INF("SM0AR: 0x%x \t(destination)\n",
dma_stm32_read(ddata, DMA_STM32_SM0AR(id)));
SYS_LOG_INF("SM1AR: 0x%x \t(destination (double buffer mode))\n",
LOG_INF("SM1AR: 0x%x \t(destination (double buffer mode))\n",
dma_stm32_read(ddata, DMA_STM32_SM1AR(id)));
SYS_LOG_INF("SFCR: 0x%x \t(fifo control)\n",
LOG_INF("SFCR: 0x%x \t(fifo control)\n",
dma_stm32_read(ddata, DMA_STM32_SFCR(id)));
}
@ -249,7 +251,7 @@ static void dma_stm32_irq_handler(void *arg, u32_t id)
stream->dma_callback(stream->dev, id, 0);
} else {
SYS_LOG_ERR("Internal error: IRQ status: 0x%x\n", irqstatus);
LOG_ERR("Internal error: IRQ status: 0x%x\n", irqstatus);
dma_stm32_irq_clear(ddata, id, irqstatus);
stream->dma_callback(stream->dev, id, -EIO);
@ -277,7 +279,7 @@ static int dma_stm32_disable_stream(struct dma_stm32_device *ddata,
/* After trying for 5 seconds, give up */
k_sleep(K_SECONDS(5));
if (count++ > (5 * 1000) / 50) {
SYS_LOG_ERR("DMA error: Stream in use\n");
LOG_ERR("DMA error: Stream in use\n");
return -EBUSY;
}
}
@ -319,7 +321,7 @@ static int dma_stm32_config_devcpy(struct device *dev, u32_t id,
DMA_STM32_SCR_MINC;
break;
default:
SYS_LOG_ERR("DMA error: Direction not supported: %d",
LOG_ERR("DMA error: Direction not supported: %d",
direction);
return -EINVAL;
}
@ -373,7 +375,7 @@ static int dma_stm32_config(struct device *dev, u32_t id,
}
if (config->head_block->block_size > DMA_STM32_MAX_DATA_ITEMS) {
SYS_LOG_ERR("DMA error: Data size too big: %d\n",
LOG_ERR("DMA error: Data size too big: %d\n",
config->head_block->block_size);
return -EINVAL;
}

4
tests/drivers/dma/chan_blen_transfer/prj.conf
View File

@ -1,4 +1,4 @@
CONFIG_DMA=y
CONFIG_ZTEST=y
CONFIG_SYS_LOG=y
CONFIG_SYS_LOG_DMA_LEVEL=1
CONFIG_LOG=y
CONFIG_DMA_LOG_LEVEL_INF=y

4
tests/drivers/dma/loop_transfer/prj.conf
View File

@ -1,4 +1,4 @@
CONFIG_TEST=y
CONFIG_DMA=y
CONFIG_SYS_LOG=y
CONFIG_SYS_LOG_DMA_LEVEL=1
CONFIG_LOG=y
CONFIG_DMA_LOG_LEVEL_INF=y