Change the drivers's compatible from atmel,sam-tc to atmel,sam-tc-qdec.
The atmel,sam-tc should be reserved for the future counter driver.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
These compatibles don't match the dt-schema regular expression for
compatible properties that we'd like to support in Zephyr because they
do not begin with a letter.
Use linaro, as a vendor prefix to make them compliant. Update the
release notes since out of tree users will need to keep up.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This patch adds a label property to the GPIO LED parent node and fixes
the label property description of the child node. Indeed it is the label
of a parent node which can be used as device_get_binding() parameter to
retrieve the LED device, and not the one of a child node.
In addition, this patch sets both this properties as not required
because they are not.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a label property to the PWM LED parent node and fixes
the label property description of the child node. Indeed it is the label
of a parent node which can be used as device_get_binding() parameter to
retrieve the LED device, and not the one of a child node.
Fixes#34275
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
STM32 internal temperature sensor driver.
This sensor can be used to measure the temperature of the CPU
and its surroundings.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
Enable FlexSPI NOR flash driver with XIP build options.
Configure FlexSPI pins, update board documentation.
Add FlexSPI NOR flash dts node for mimxrt685_evk.
Enable flash storage by adding partition to dts file.
Using last 1MB for storage, and reserving 63MB for code.
Signed-off-by: Saurabh Jagdhane <saurabh.jagdhane@nxp.com>
Adding Reset and Write-protect pins initialization during AT45 driver
start-up. Usually these pins are driven high when not used.
The AT45 device incorporates an internal power-on reset circuit, so
there is no initial on-off reset sequence.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
Implementation of the Bosch M_CAN IP driver.
This driver is just the base for a specific SoC implementation.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
ADC emulator is designed to be used in tests on native_posix board. It
supports 1-16 bit resolution range and all GAINs from enum adc_gain.
Reference voltages and number of emulated channels are set through dts.
Using special API from drivers/adc/adc_emul.h it is possible to set
constant voltage value returned by given ADC channel or set custom
function which allows to simulate complex output.
Also reference voltages can be changed in runtime using the API.
The CL also includes:
- Add adc definitions of ADC emulator in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
- Add test for ADC emulator API in tests/drivers/adc/adc_emul/
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
add dts bingings for dma usage
add dts support for adc with edma and hwtrigger
add a periodic_trigger feature to dts
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Renesas has Serial Communication Interface with
FIFO (SCIF) hardware block which allow asynchronous and
synchronous serial communication. The SCIF has 16-stage FIFO
buffers separately for transmissions and reception.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.
Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Remove reset pin requirement from devicetree as this
is not required for modem functionality, and is not
used in the driver anyways.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
The MAX17262 is an ultra-low power fuel-gauge IC which implements the
Maxim ModelGauge m5 algorithm. The IC monitors a single-cell battery
pack and supports internal current sensing for up to 3.1A pulse
current. The IC provides best performance for batteries with 100mAhr
to 6Ahr capacity.
Signed-off-by: Matija Tudan <mtudan@mobilisis.hr>
Add pinctrl-0 as being required on NXP Kinetis DTS bindings for I2C,
FTM, UART, and DSPI related devices.
Other devices like ethernet and CAN are utilized outside of just the
Kinetis family and thus we can not require pinctrl-0 property for them
at this time.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add specific binding for stm32f100 pll which differs from existing
stm32f1 and stm32f105 specific pll binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Automatic collision detection for half-duplex mode can be enabled
by setting `collision-detection` proprety for uart hardware
in the dts file. If the transmitted bit does not match the received
bit an error is raised. This is useful in RS-485 half-duplex mode.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Add binding fro stm32wl-rcc.yaml that derivates from stm32wb-rcc.
Additionally update stm32wb-pll-clock.yaml to be used as well
for stm32wl series and add missing div-m property.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add bindings for F0/F3/G0/G4 clocks.
Introduce new rcc binding "st,stm32f0-rcc" binding
that describes RCC hardware blocks that don't have
"apb2-prescaler".
This binding also applies to G0.
Binding "st,stm32f0-pll-clock" is used for both F0
and F3 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PLL bindings for STM32F1 devices.
- Main PLL binding for STM32F1 non connectivity lines
- Main and PLL2 binding for Connectivity lines (F105/F107)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Exit latency is the maximum time required by a CPU to transition from
a specific idle state to active state. This information is going to be
used to properly configure the wake up event in order to the system be
able to execute the next scheduled task.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
NPCX PWM supports output buffet select to push-pull or open-drain. Add
output buffer select option 'drive-open-drain' in devicetree for NPCX
PWM. If set, the PWM output will be configured as open-drain. If not
set, defaults to push-pull.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
These changes turn out to have been incompatible with the way pinctrl
drivers are going to work, so we need to go back to what we had before
until we can agree on a better approach.
Squash of the following reverts:
Revert "boards: nrf: fix deprecated I2C properties"
This reverts commit 2a4ac9ac02.
Revert "samples: switch nrf overlays to sda-gpios, scl-gpios"
This reverts commit 01bb08e7d8.
Revert "boards: nrf: switch to sda-gpios, scl-gpios"
This reverts commit 17a66304c4.
Revert "i2c: nordic: switch to phandle arrays for pinmux"
This reverts commit 821c03a14a.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When 1.8V is disabled, sdhc can only
communicate at low speed. But this can
save the external circuit for switching
between 3.3V and 1.8V, which is very
practical in costdown scenarios.
Signed-off-by: Frank Li <lgl88911@163.com>
Some SPI NOR devices, particularly Atmel and SST, power-up with block
protect bits set in the status register. These bits must be cleared
before any erase or program operation can succeed. However, blindly
clearing bits in SR is wrong as some of these are non-volatile and
control chip behavior, including quad-enable.
Add a devicetree flag to identify device-specific BP bits in the status
register that should be cleared on startup only for devices that need
them, and when set do the clear during initialization.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
