dts/bindings: clocks: Add clocks bindings for stm32h7 series

Add clocks related stm32h7 specific bindings:
- stm32h7-hsi-clock
- stm32h7-pll-clock
- stm32h7-rcc

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>

dts/bindings/clock/st,stm32h7-hsi-clock.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 HSI Clock
+
+compatible: "st,stm32h7-hsi-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    hsi-div:
+      type: int
+      required: true
+      description: |
+        HSI clock divider. Configures the output HSI clock frequency
+      enum:
+        - 1 # hsi_clk = 64MHz
+        - 2 # hsi_clk = 32MHz
+        - 4 # hsi_clk = 16MHz
+        - 8 # hsi_clk = 8MHz

dts/bindings/clock/st,stm32h7-pll-clock.yaml

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+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32H7 devices
+
+  It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
+  Only PLL1 and PLL3 are supported for now.
+
+  These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
+  an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
+    f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
+    f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
+
+      with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
+
+  The PLL output frequency must not exceed 80 MHz.
+
+compatible: "st,stm32h7-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for PLLx
+          input clock
+          Valid range: 0 - 63
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCOx
+          Valid range: 4 - 512
+
+    div-p:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_p_ck
+          Valid range: 1 - 128
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_q_ck
+          Valid range: 1 - 128
+
+    div-r:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_r_ck
+          Valid range: 1 - 128

dts/bindings/clock/st,stm32h7-rcc.yaml

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+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Reset and Clock controller node for STM32H7 devices
+  This node is in charge of system clock ('SYSCLK') source selection and
+  System Clock Generation.
+
+  Configuring STM32 Reset and Clock controller node:
+
+  System clock source should be selected amongst the clock nodes available in "clocks"
+  node (typically 'clk_hse, clk_csi', 'pll', ...).
+  As part of this node configuration, SYSCLK frequency should also be defined, using
+  "clock-frequency" property.
+  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
+  prescaler properties.
+  Here is an example of correctly configured rcc node:
+  &rcc {
+           clocks = <&pll>;  /* Set pll as SYSCLK source */
+           clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
+           d1cpre = <1>;
+           hpre = <1>;
+           d1ppre = <1>;
+           d2ppre1 = <1>;
+           d2ppre2 = <1>;
+           d3ppre = <1>;
+  }
+
+  Specifying a gated clock:
+
+  To specify a gated clock, a peripheral should define a "clocks" property encoded
+  in the following way:
+  ... {
+           ...
+           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+           ...
+  }
+  After the phandle referring to rcc node, the first index specifies the registers of
+  the bus controlling the peripheral and the second index specifies the bit used to
+  control the peripheral clock in that bus register.
+
+compatible: "st,stm32h7-rcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+    clock-frequency:
+      required: false
+      type: int
+      description: |
+        default frequency in Hz for clock output
+
+    d1cpre:
+      type: int
+      required: false
+      enum:
+        - 1
+      description: |
+          D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
+          lower than SYSCLK frequency (actual core frequency).
+          Zephyr doesn't make a difference today between these two clocks.
+          Changing this prescaler is not allowed until it is made possible to
+          use them independently in Zephyr clock subsystem.
+
+    hpre:
+      type: int
+      required: false
+      description: |
+          D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 64
+        - 128
+        - 256
+        - 512
+
+    d1ppre:
+      type: int
+      required: false
+      description: |
+          D1 domain, APB3 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d2ppre1:
+      type: int
+      required: false
+      description: |
+          D2 domain, APB1 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d2ppre2:
+      type: int
+      required: false
+      description: |
+          D2 domain, APB2 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d3ppre:
+      type: int
+      required: false
+      description: |
+          D3 domain, APB4 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+clock-cells:
+  - bus
+  - bits