STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simple driver that allows one to choose the clock speed of xtensa cores.
It's basically a shim layer on top of SOC level driver.
Also, a really simple test case was added, mainly to ensure things are
build and are sane.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This commit adds a check for the validity of the "sub_system" param in
clock_control_on.
While for clock_control_off there was a check if the clock_subsytem
parameter is in range of STM32_PERIPH_BUS_MIN and STM32_PERIPH_BUS_MAX
this check was missing for clock_control_on.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
-Kept getting an error on STM32g0xx chips that didn't have q-divisor.
-Changed to set prescaler only if it's being used.
Signed-off-by: Dan Higginbotham <daniel@dedesignworks.com>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Checking that provided pclken->bus fits bus range in
clock_control_get_rate() is wrong as it could actually be a source
clock and hence not belong to this range.
Also, this kind of check is just not needed since this function should
not be used before call to clock_control_on() or clock_control_configure()
which do the required verification.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This PR Fixes the Audio PLL Rate Calculation (there was an additional
divide / 8 which is not necessary and does not appear in similar
calculations in example code from the SDK).
Additionally, it adjusts the SAI .dtsi to more correctly configure the
mclk rate, and adds comments specifying what the regististers mean.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Similarly to what was done on U5 and H7 clock_control drivers, enable
device clock source selection.
This is done by:
-providing implementation for clock_control_configure().
-updating clock_control_get_rate() to support various possible clock
sources (SYSCLK, PLLCLK, LSE, LSI, HSI, HSE).
-providing enable_clock() to verify requested clock source exists and
is enabled.
-adding LSI and LSE device tree based initialization to
set_up_fixed_clock_sources().
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename and factorize clock source bindings accessors by moving them
in common header file stm32_clock_control and remove them from
include/dt-bindings/clock/stm32XY_clock.h files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use `DT_REG_ADDR_BY_NAME` and `DT_REG_SIZE_BY_NAME` to access register
properties from dts.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. If we gate the eSPI clock at initialzation, it
will make the eSPI configuration which established by previous image
break and lost the communication between EC and host.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Implement SDHC driver for NXP USDHC peripheral, supporting all api calls
available in the sdhc driver. This implementation leverages NXP's HAL,
and simply implements a shim layer over the HAL itself.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is the actual hclk freq (ie core clock);
Remove use of intermediate new_hclk_freq to fix and simplify code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some specific F1 variants don't handle flash latency.
Put flash latency dealing code under dedicated switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review code style in set_up_fixed_clock_sources() for better
readability.
Use of 'if (IS_ENABLED(STM32_MSI_ENABLED))' inside '#if STM32_MSI_ENABLED'
is redundant but intentional as it is in line with remaining part of the
function (HSE/HSI cases).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Group fixed clocks inits in a unique set_up function.
Each clock is initialized depending on its dts status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simplify and clean up driver code using STM32 clocks DT based macros.
Added STM32_FLASH_PRESCALER macro for this purpose.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Factorize setting of frequency for busses.
Additionally, factorize SysCoreClock update.
The operations are now done twice in case of PLL since they are part
of LL utils PLL configuration function, but they are removed in next
commits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Take advantage of previous work to configure PLL and remove
usage of LL_PLL1_ConfigSystemClock_FOO utils functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that fixed clocks are enabled in a single function, a
bunch of functions could now be removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move fixed clocks initialization to a single function.
Benefit is they could now be enabled independently of the
main clock configuration based on dts status and then be
used by peripherals even is not part of the main clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Flash latency setting could be factorized in a single location,
rather than split in each clock setting function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move prescaler settings to the clock_control_init function.
At this step they will be set up twice in PLL case, this will
be fixed in a next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
