LVGL eats a considerable amount of flash, so tests may fail on platforms
that meet all requirements but that have a low amount of flash, e.g.
nucleo_g071rb. Set min_flash for all cases to 250K (result of some quick
experimentation). Also update minimum ram to exclude platforms that
cannot run Zephyr + LVGL (e.g. those with just 16K).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
'display' harness doesn't exist, so replace it with 'none' to make
things more clear. It is required so that test is not run e.g. on CI,
test would timeout because the GUI is left ON forever.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simplify sample.yaml by just adding a single test case. In future
commits, test case will be refined to be based on DT filters so that it
is made more generic.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PAN1780 evaluation board is a development tool for the nRF52840
from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The PAN1781 evaluation board is a development tool for the nRF52820
from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The PAN1782 evaluation board is a development tool for the nRF52833
from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The PAN1770 evaluation board is a development tool for the nRF52840
from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The test_adc.c still have hardcoded information on a board basis,
that need to be added manually.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
Some of the Panasonic's evaluation boards have limited amount of pins.
So not all arduino pins can be occupied and not all shields are
compatible.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
Panasonic's reduced Arduino header is based on the Arduino UNO layout.
The main difference is that some pins are not available due to the
lack of pins on the Panasonic module.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
Move driver to use gpio_dt_spec for GPIO interrupt handling.
Added check to vcnl4040_trigger_set to handle case of trigger
mode enabled but the devicetree doesn't have an int_gpios property.
Also, moved up the checking/handling of gpio port device in
vcnl4040_trigger_init so that if we error out its before we
setup any threads and such.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET_ONE instead of device_get_binding as we
work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Fix duplicate ID for systemview. Remove k_timer_user_data_set as it is
not being tracing and uses a duplicate ID like k_sem_reset.
Fixes#46541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fix wrong control register address used in uart_altera_jtag_init
function which caused memory corruption.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
By default ARCH_IRQ_VECTOR_TABLE_ALIGN and ARCH_SW_ISR_TABLE_ALIGN are
set to 0. Use a more proper value.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This test is based on the wrong assumption that the IRQ vector table
symbols are always placed by the linker script also when
CONFIG_GEN_IRQ_VECTOR_TABLE is not actually set.
This is of course broken with the reworked mechanism of the IRQ vector
table placement.
Fix the test by reintroducing the old behaviour by forcefully
reinstating the symbols in the linker script.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The generation of the software ISR table and the IRQ vector table
(respectively generated by CONFIG_GEN_SW_ISR_TABLE and
CONFIG_GEN_IRQ_VECTOR_TABLE) should (in theory) go through three stages:
1. A placeholder table is generated in arch/common/isr_tables.c and
placed in an orphaned .gnu.linkonce.{irq_vector_table, sw_isr_table}
section
2. The real table is generated by arch/common/gen_isr_tables.py (creating
the build/zephyr/isr_tables.c file)
3. The real table is un-orphaned by moving it in a proper section with a
proper alignment
While all the steps are done automatically for the software ISR table,
for the IRQ vector table each architectures must take care of modiying
its own linker script to place somewhere the generated IRQ vector table
(basically step 3 is missing).
This is currently only done for 2 architectures: Cortex-M (ARMv7) and
ARC. But when another architecture tries to use the IRQ vector table,
the linker complains about that. For example:
Linking C executable zephyr/zephyr.elf
riscv64-zephyr-elf/bin/ld.bfd: warning: orphan section
`.gnu.linkonce.irq_vector_table' from
`zephyr/CMakeFiles/zephyr_final.dir/isr_tables.c.obj' being placed in
section `.gnu.linkonce.irq_vector_table'
In this patch we introduce a new CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN to
support the architectures requiring a special alignment for the IRQ
vector table and we also introduce a way to automatically place the IRQ
vector table in place in the same way it is done for the ISR software
table.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
On platforms where reset vector catch is not possible
it is useful to have a compile-time option to spin
at the reset vector allowing a debugger to be attached
and then to manually resume execution.
Define a config option for arm64 to spin at the
reset vectdor so a debugger can be attached.
Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.
Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.
Update the npcx9m6f_evb instructions now that the filename is implicit.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Add clang-format to the requirements-extras.txt and require a version
compatible with the configuration options present in the .clang-format
file.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a maintainership section in the ext-source template, forcing future
contributors to identify one or more maintainers.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The STM32H7A3 SoC has 64 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Move to use DEVICE_DT_GET_ONE instead of device_get_binding as we
work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Complete the remote initiated version exchange if a LL_VERSION_IND is
received while already having responded in an earlier version exchange
procedure.
Clarify comment regarding how to handle this invalid behaviour.
This has been seen when running the LL/CON/CEN/BI-12-C test on EBQ.
Signed-off-by: Thomas Ebert Hansen <thoh@oticon.com>
Calculation of the DLE related parameters (rx/tx octets and time) depend
on the actual phy in use. For this reason the PHY settings must be
initialised before doing the DLE parameter calculations
Signed-off-by: Andries Kruithof <andries.kruithof@nordicsemi.no>
STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
* Convert test suite declaration to `ZTEST_SUITE()`
and test case declaration to `ZTEST()`.
* add `CONFIG_ZTEST_NEW_API=y` to prj.conf
Fixes#46793
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
On remote terminate on central the conn clean-up would happen before ack
of terminate ind was sent to peer.
Now clean-up is 'postponed' until subsequent event.
Also now data tx is paused on rx of terminate ind to ensure no data is
tx'ed after rx of terminate ind
Signed-off-by: Erik Brockhoff <erbr@oticon.com>
On disconnect with refactored LLCP, if data tx is paused,
possibly 'waiting' tx nodes would not get released.
Signed-off-by: Erik Brockhoff <erbr@oticon.com>
On FVP platform, when parameter 'bp.refcounter.use_real_time' is set
to 1, cntvct_el0 isn't count from 0 and may cause overflow issue in
first timer compare interrupt.
'bp.refcounter.use_real_time' is 0 by default.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Fast hardware with slow timer hardware can trigger and enter an
interrupt and reach 'sys_clock_set_timeout' before the counter has
advanced.
That defeats the "round up" logic such that we end up scheduling
timeouts a tick too soon (e.g. if the kernel requests an interrupt
at the "X" tick, we would end up computing a comparator value
representing the "X-1" tick!).
Choose the bigger one between 1 and "curr_cycle - last_cycle" to
correct.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Only apply change to effective DLE times if current max times are too
small to accommodate. Similar to legacy implementation
Update unit tests to new DLE ntf behavior
Signed-off-by: Erik Brockhoff <erbr@oticon.com>
The magnetometer data read from AK9863 is assumed to be big endian
(like the accelerometer & gyroscope data).
However it is in little endian, which means the appropriate byteorder
function is sys_le16_to_cpu().
See the MPU925 register map:
https://3cfeqx1hf82y3xcoull08ihx-wpengine.netdna-ssl.com/wp-content/uploads/2017/11/RM-MPU-9250A-00-v1.6.pdf
At 5.6 HXL to HZH: Measurement Data
Signed-off-by: Loris Schmit <loris.schmit@inovex.de>
Some text in help section was documenting the compatibility of driver
variants with stm32 series.
This is duplicate of information versus device tree which should be
used as single source of information for hardware description.
Remove these lines, so we don't have to touch this driver each time
a series is added.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some TFM samples run different test suites/cases based on
which configurations are set.
Enumerate more of these.
For samples/tfm_integration/tfm_psa_test,
add the following new build configurations:
* Add CONFIG_TFM_PSA_TEST_STORAGE
* Add CONFIG_TFM_PSA_TEST_CRYPTO
* Add CONFIG_TMF_PSA_TEST_INITIAL_ATTESTATION
For samples/tfm_integration/tfm_regression_test,
add this to all build configurations:
* Add CONFIG_TFM_PARTITION_PROTECTED_STORAGE
* Add CONFIG_TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
* Add CONFIG_TFM_PARTITION_CRYPTO
* Add CONFIG_TFM_PARTITION_INITIAL_ATTESTATION
* Add CONFIG_TFM_PARTITION_PLATFORM
* Add CONFIG_TFM_PARTITION_AUDIT_LOG
And build the above for CONFIG_TFM_IPC as well.
Signed-off-by: Torstein Grindvik <torstein.grindvik@nordicsemi.no>
They may be disabled in some environments (such as Gentoo based
developer mode on Chromebooks). Use extended regular expressions
instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
