don't use global buffers for reg_read and reg_write,
so we only need to rely on the spi drivers lock and
don't have to use our lock.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The requested SPI clock rate and the actual rate that is set can be
different depending on the peripheral clock and divisors available to
the SPI peripheral. For some MAX32 SoCs, actual rate ended up being
higher than the devicetree setting. This would then cause latency tests
to fail as transfers finish earlier than minimum expected duration.
Update the test frequency values in several MAX32 board overlays to pass
latency tests.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
spi_configure was returning HAL error codes that are incompatible with
Zephyr error definitions straight back to the caller. Replace these with
error codes that Zephyr can correctly interpret.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Driver was not handling SPI word sizes other than 8 bits. Apply DFS
shift wherever necessary to support non 8-bit transfers.
DMA mode cannot support word sizes that are less than 8 bits so return
-ENOTSUP if word size less than 8-bits is required.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
In the BAP Broadcast Sink implementation the sync request,
the BIGInfo and the broadcast code can come in any other.
Currently the btp_bap_broadcast_sink_bis_sync would reject
the request if it came before the BIGInfo, but will now
instead store the request and then apply it once the BIGInfo
has been received, as there is not BIGInfo BTP event that the
caller can use.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Nicla Vision datasheet is referring to the 8-bit wire address (0x52) for
the VL53L1X sensor, so that's likely what ended up being used in the
board's devicetree. However, it's the 7-bit I2C address that should be
used so fix that by changing the I2C address to 0x29. Successfully
tested on actual hardware.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Avoid redeclaring 'err' inside a nested block, which shadowed the outer
definition.
This cleanup prevents confusion and potential logical bugs.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Avoid redeclaring 'err' inside a nested block, which shadowed the outer
definition.
This cleanup prevents confusion and potential logical bugs.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Avoids shadowing the outer 'err' variable by reusing it instead of
redeclaring a new one inside conditional blocks.
This improves clarity and prevents confusion during debugging.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Add the service_area section to the list of sections for which objcopy
is executed. As this section was missing from the resulting data image,
it prevents targets (right now, the mimxrt685s/hifi4) from booting.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
1. enable sensor/nxp,lpcmp support
2. verified samples/sensor/mcux_lpcmp
3. update the mcux_lpcmp to support different port
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Reading back the raw interrupt status from the gpio controller, provides
the interrupt mask _without_ the controller's masking registers applied.
This means that e.g. a rising edge would trigger an interrupt even on
pins that are configured for falling edge only.
Fix this by reading the "enabled" interrupt status instead of the raw
one.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
The polarity mapping was swapped such that GPIO_INT_TRIG_LOW would
translate to high, and vice versa, on the chip configuration.
Swap the polarity to fix this.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
This commit implements the gpio_get_config handle for the gpio_mspm0
driver.
NOTE: Currently only handles input/output state and not configured flags
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
Prior to this commit, writing a gpio port would completely clear
the state of given port. This commit ensures that state is kept
when writing, reading and configuring gpio ports.
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
Add a new flash for toggling runtime SFDP data fetching, and use static
devicetree properties by default. Clean up various minor items from review.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Properly configure the MAX32 SPIXF peripheral to use the SPIXF controller
for transparent memory mapped reads, and enable the SPIXF main controller
and use it for writes.
Add support for testing XIP support to the nocopy sample, which requires
flashing with OpenOCD with MAX32690 QSPI flash support.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Update common flash test and jesd216 samples to work on the
APARD32690-SL board which has MX25U6432FM2I02 on-board.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Xilinx Window Watchdog driver uses window watchdog mode. Window watchdog
timer(WWDT) contains closed(first) and open(second) window with 32bit
width each. Write to the watchdog timer within predefined window periods
of time. This means a period that is not too soon and a period that is
not too late. The WWDT has to be restarted within the open window time.
If the software tries to restart WWDT outside of open window time
period, it generates a SoC reset.
Signed-off-by: Harini T <harini.t@amd.com>
Xilinx Window Watchdog Timer IP uses window mode.
Window watchdog timer(WWDT) contains closed(first) and open(second)
window with 32 bit width each. Write to the watchdog timer within
predefined window periods of time. This means a period that is not too
soon and a period that is not too late.
The WWDT error interrupts (IRQs) occur when the watchdog timer is not
serviced within the predefined window periods. These IRQs are routed to
the Processing System Manager (PSM) error accumulator module. The PSM is
responsible for managing power and system-level errors, generating a
System on Chip (SoC) reset when a WWDT error occurs. The system reset
event is signaled as a system error for the PSM firmware to handle and a
reset output signal to the MIO/EMIO.
Signed-off-by: Harini T <harini.t@amd.com>
add bt_conn_br_switch_role and bt_conn_br_set_role_switchable to control
the role switch, add DEFAULT_ROLE_SWITCHABLE Kconfig to control the default
role switch state.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
rename gpio stepper to h bridge stepper
minor correction in stepper_stop, stepper_stop shall cancel all active
movements and should not be concerned about keeping the coils energized
or not, since that is a concern of a motion controller and not a stepper
driver.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Add and exchange global heap configuration CONFIG_HEAP_MEM_POOL_SIZE
against configuration used for auto heap calculation
CONFIG_HEAP_MEM_POOL_ADD_SIZE_ZBUS.
Add CONFIG_HEAP_MEM_POOL_ADD_SIZE_ZBUS as related configuration
Clarify that HEAP is used for zbus in a whole
Consistent naming 'Zbus'/'zbus' to 'ZBus'
Signed-off-by: Matthias Plöger <matthias.ploeger@phoenixcontact.com>
Zbus currently does only support default heap sizes.
The configuration option allows to decrease rom-footprint for embedded
applications. Adding the option to ZBus improves its flexibility and
while not increasing its complexity.
Add default of 0 value to compensate for previous cases where
HEAP_MEM_POOL_ADD_SIZE_ZBUS was defined as "".
Consistent naming 'Zbus'/'zbus' to 'ZBus'
Signed-off-by: Matthias Plöger <matthias.ploeger@phoenixcontact.com>
On it8xxx2, there are VW transmitted registers indicating that VW signal
has been transmitted to host. This patch checks the register to ensure
successful transmission of VW state change.
fixes: #89298
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Added driver and binding file for samd5x dac peripheral, the already
implemented dac_sam0.c lacks the configuration registers for this
microcontroller family and is fixed to only have one dac channel output,
also, the code gets too bulky when adding the samd5x dac configuration
using preprocessor directives that’s why I moved the implementation to its
own file.
Added dac to the supported list of same54_xpro.yaml, fixed Kconfig.samd5x
help spacing, added board defines to test_dac.c and test it out with
twister script on board.
Signed-off-by: Rafael Aldo Hernández Luna <aldo.hernandez@daikincomfort.com>
Adds sample showing i2c+gpio endpoint bindings in use.
Provides an overlay for the frdm-mcxn947 development board using JP8
pins for i2c and gpio connectivity.
The sample periodically sends a "ping" message to the bus controller and
prints out any messages it receives itself.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a sample application that can act as the bus owner using
i2c+gpio mctp binding.
Provides an overlay for the frdm-mcxn947 using JP8 pins for i2c and
gpio.
It attempts to send a "ping" message to all endpoints while accepting
string messages from endpoints to print out.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a I2C+GPIO Target device binding for MCTP communication over I2C.
The binding requires an i2c bus and gpio pin, along with a specified I2C
and endpoint address pair. These are then used to create an MCTP binding
which can be used to communicate in a peer to peer manner among other
MCTP endpoints.
Each message transmit signals to the bus controller using a GPIO logical
high and is unset on transmission completion. Pending transmitters are
queued using a semaphore avoiding memcpy being needed to asynchronously
transmit mctp pktbufs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a custom MCTP binding for an I2C bus controller using GPIO signaling
for write requests rather than mode switching.
This binding operates a lot like the I3C binding specification DMTF has
for MCTP. The controller expects to receive interrupts (from GPIO pins)
and upon getting an interrupt read a message from the I2C target device.
The macro does a lot of the heavy lifting to setup all the state needed
for capturing GPIOs, being able to do asynchronous reads/writes, and
such. The entire controller works using state machines driven by
interrupts leading to low latency and clear ram costs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Unfortunately libc malloc/free are wrapped with a sys_mutex which is
troublesome for mctp as we likely want to allocate from interrupts in many
cases.
Supply mctp with a dedicated heap initialized and assigned at boot
saving applications a step. The default size is quite small and works
well so long as messages are small.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Driver simply registered itself without setting the level based on the
I2C Kconfig which wasn't quite right, need the log level set based on
the Kconfig for I2C.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
IUT works as a l2cap server with basic mode. The peer device,
l2cap client with basic mode, is a PC with running `bumble` on it.
This test only performs the function of L2CAP basic mode.
Support multiple l2cap enerties in new shell l2cap_br,
which may support more test function.
In the test suite , there are two groups in test cases.
Group 1 Including case1-case8 focuses on connection and
disconnection around l2cap. The impact of active and passive
acl connectivity, disconnectivity and authentication as well as
disconnection from ACL without l2cap disconnect is tested.
Group2 Including case9-case14 revolves around the basic
parameters of L2CAPserver configuration, data transfer.
Case 9: Test l2cap connection with max MTU(0xffff).But the max mtu
which the stack supports is (CONFIG_BT_BUF_ACL_RX_SIZE - 4U = 196).
Case 10: Test l2cap connection with min MTU(0x30),set server mtu = 48,
client mtu = 0xffff, l2cap connect successfully,
client mtu = 0xffff, server mtu = 48.
Case 11: Test l2cap connection with min MTU(0x30),set server mtu < 48,
client mtu = 0xffff, l2cap connect fail.
Case 12: Test l2cap connection with min MTU(0x30),set server mtu = 48,
client mtu<48,l2cap connect successfully,
client mtu=48,server mtu=48.
Case 13: Test l2cap connection with invaild PSM.
Case 14: Test l2cap multi_channel connection and data tranfer.
Case 15: Stress Test. Repeat l2cap connect, disconnect operation.
Case 16: Stress Test. Repeat data transfer in a single connection.
In Case 15 and 16, if enlarging STRESS_TEST_MAX_COUNT and test fail,
you can enlarge timeout in testcase.yml.
test_l2cap_server.py is a file containing real test cases.
test_l2cap_common.py is a common file. It encapsulates some
test function functions that are commonly used for test cases.
Signed-off-by: Cheng Chang <cheng.chang@nxp.com>
Now in other mode rather than basic mode, configuration parameters
include MTU, Flush Time and QoS have been checked.
But in basic mode, they also need to be checked, so the code about this
should not be controlled by macro CONFIG_BT_L2CAP_RET_FC.
Signed-off-by: Cheng Chang <cheng.chang@nxp.com>
Reverts commit 5700ffe9ad.
Not required anymore as the CONFIG_BOOT_MAX_IMG_SECTORS
is fixed by the mcuboot at 4096.
Add the corresponding overlay file.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Run the sample to execute in place on the external flash of the
stm32h573 disco kit.
with_boot is build and linked for the external flash.
Download the mcuboot zephyr.bin in internal memory.
Download the with_mcuboot zephyr.signed.bin in external memory.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the XSPI 2 which is an octoSPI connection to a octo NOR flash
mx25lm51245 on the stm32h573i_dk disco kit.
Define the partition on the 64MBytes space of the external flash.
Use the STM32Cube programmer to flash with the corresponding
external loader for XiP mode.
Removing usb_device will avoid test feature for that board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The flash_stm32_xspi driver should not initialize the xspi,
if this one is being use to execute in Place : the init is skipped.
This mode is identified with the CONFIG_STM32_APP_IN_EXT_FLASH.
Checking the memory mapped mode bit is possible when the xspi
peripheral clock is not off (stm32h5 has no clock_control_get_status API)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
