Allow STM32 ADC driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit. Also remove inclusion of zephyr/arch/cache.h that is not
needed at all.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Added support for differentail or single ended setup.
Reading resolution form dt - adc spec.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
This commit changes to use ambiq hal power control APIs
to replace the previous register settings to power on
ambiq drivers.
Signed-off-by: Hao Luo <hluo@ambiq.com>
Extend support in dt bindings and in the driver to allow use of
AIN8 to AIN13 analog inputs.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Initial AD405X driver supporting sampling, averaging
and burst averaging operation modes. Configurable
without interrupts or with device ready and
data ready interrupt.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Currently, in Renesas adc driver, channel_count is used
as the maximum index of the channels can be supported.
However, the value input in dts of "channel_count"
represents the total number of supported channels.
After consideration, we have decided to remove this
reduntant property.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Select Reference voltage of 900mV for ADC on nRF54L20pdk.
Add ADC to the list of supported peripherals.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Extend nrf saadc device driver with pm device runtime support.
To preserve previous behavior:
* if pm device is disabled, saadc is resumed on sampling start
and suspended when sampling done.
* if pm device is enabled only, saadc does nothing on
sampling start/stop. its resumed on init.
* if pm device runtime is enabled, saadc is got on
sampling start, and put on sampling stop.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
On STM32N6, the register holding the data is 32 bits and DMA must operate
in word transfer to work properly. So we change the type of the buffer in
which we store the ADC data from uint16_t to uint32_t for N6.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added the test configuration for nRF54L20 for the following tests:
- adc_api
- adc_error_cases
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Make use of ABUS support in the pinctrl driver to allocate
analog buses, rather than hard-coding bus 0 in the ADC driver.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
In case channel_setup is called with a new attenuation
config, make sure previous calibration scheme is deleted properly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Clang run for code formatting and calibrationc control for
repeated calls at channel_setup().
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Driver update to support newer HAL versions.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Marek Matej <marek.matej@espressif.com>
`adc_read_async` is documented as supporting the `async` signal as NULL.
Update the emulator to no longer block until completion when
`adc_read_async` is called in this situation.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The AD4114 is a low power, low noise, 24-bit, sigma-delta ADC.
This driver allows to use it with the Zephyr ADC API. It uses
the continuous acquisition ADC feature.
This ADC allows many configutations, but this driver uses it as the
most generic way :
- each can channel can be enable or disable using the device
tree configuration
- configure two setups (one for unipolar inputs, one for bipolar inputs)
- use an external clock
Signed-off-by: Pierrick Curt <pierrickcurt@gmail.com>
The SAM0 ADC has an internal register to divide the accumulated results
of oversampling the ADC by the amount of samples collected. This value
has to be set by the driver and was missing.
Signed-off-by: Patrick Günzel <patrick.guenzel@kinexon.com>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fixed bug calculating offset of registers after unused space in the ADC
register space for the SZ package parts.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
ADS131M02 is Texas Instruments 2-channel, 24-Bit differential
input ADC which support wide range datarate.
Driver add support for adc read, channel configure, adc sampling
mode configuration and power management.
[1]. https://www.ti.com/lit/ds/symlink/ads131m02.pdf
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu drv adc update driver with string
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.
Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).
Last, this change enables the DMA support for F1x ADC.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
